| 臺大學術典藏 |
2020-06-11T06:33:08Z |
A high-throughput and arbitrary-distribution pattern generator for the constrained random verification
|
Wu, B.-H.;Yang, C.-J.;Huang, C.-Y.; Wu, B.-H.; Yang, C.-J.; Huang, C.-Y.; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:33:08Z |
Match and replace: A functional ECO engine for multierror circuit rectification
|
Huang, S.-L.;Lin, W.-H.;Huang, P.-K.;Huang, C.-Y.; Huang, S.-L.; Lin, W.-H.; Huang, P.-K.; Huang, C.-Y.; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:33:08Z |
An ultrasynchronization checking method with trace-driven simulation for fast and accurate MPSoC virtual platform simulation
|
Yeh, Y.-F.;Lin, H.-C.;Huang, C.-Y.; Yeh, Y.-F.; Lin, H.-C.; Huang, C.-Y.; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:33:07Z |
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method.
|
Yeh, Yu-Fu;Huang, Chung-Yang;Wu, Chi-An;Lin, Hsin-Cheng; Yeh, Yu-Fu; Huang, Chung-Yang; Wu, Chi-An; Lin, Hsin-Cheng; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:33:07Z |
Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques
|
Wu, B.-H.;Yang, C.-J.;Tso, C.-C.;Huang, C.-Y.R.; Wu, B.-H.; Yang, C.-J.; Tso, C.-C.; Huang, C.-Y.R.; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:33:06Z |
Automatic abstraction refinement of TR for PDR
|
Fan, K.;Yang, M.-J.;Huang, C.-Y.; Fan, K.; Yang, M.-J.; Huang, C.-Y.; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:33:06Z |
Adaptive interpolation-based model checking
|
Lai, C.-Y.;Wu, C.-Y.;Huang, C.-Y.R.; Lai, C.-Y.; Wu, C.-Y.; Huang, C.-Y.R.; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:33:05Z |
Fundamentals of Algorithms
|
Huang, C.-Y.;Lai, C.-Y.;Cheng, K.T.; Huang, C.-Y.; Lai, C.-Y.; Cheng, K.T.; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:33:05Z |
Fast and accurate MPSoC virtual platform simulation with parallel out-of-order execution approach
|
Yeh, Y.-F.;Lin, S.-Y.;Huang, C.-Y.; Yeh, Y.-F.; Lin, S.-Y.; Huang, C.-Y.; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:46:44Z |
SoC HW/SW Verification and Validation
|
Yu-Fan Yin; Chih-Jen Hsu; Thomas B. Huang; Ting-Mao Chang; CHUNG-YANG HUANG; Chung-Yang (Ric) Huang |
| 臺大學術典藏 |
2018-09-10T08:46:44Z |
Speeding Up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method
|
Yu-Fu Yeh; Chung-Yang (Ric) Huang; Chi-An Wu; Hsin-Cheng Lin; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:18:34Z |
A Unified Multi-Corner Multi-Mode Static Timing Analysis Engine
|
Chin-Chia Nien;Shih-Heng Tsai;Chung-Yang (Ric) Huang; Chin-Chia Nien; Shih-Heng Tsai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:18:34Z |
Speeding Up SoC Virtual Platform Simulation by Data-Dependency-Aware Synchronization and Scheduling
|
Kuen-Huei Lin;Siao-Jie Cai;Chung-Yang (Ric) Huang; Kuen-Huei Lin; Siao-Jie Cai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:18:34Z |
Formal Deadlock Checking on High-Level SystemC Designs
|
Chun-Nan Chou;Chang-Hong Hsu;Yueh-Tung Chao;Chung-Yang (Ric) Huang; Chun-Nan Chou; Chang-Hong Hsu; Yueh-Tung Chao; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:18:34Z |
A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques
|
Bo-Han Wu;Chun-Ju Yang;Chung-Yang (Ric) Huang;Jie-Hong (Rol;) Jiang; Bo-Han Wu; Chun-Ju Yang; Chung-Yang (Ric) Huang; JIE-HONG JIANG; Jie-Hong (Rol; ) Jiang; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:18:34Z |
Automatic Constraint Generation for Guided Random Simulation
|
Hu-Hsi Yeh;Chung-Yang (Ric) Huang; Hu-Hsi Yeh; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:18:33Z |
To SAT or Not to SAT: Scalable Exploration of Functional Dependency
|
Jie-Hong R. Jiang;Chih-Chun Lee;Alan Mishchenko;Chung-Yang (Ric) Huang; Jie-Hong R. Jiang; Chih-Chun Lee; Alan Mishchenko; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T07:42:21Z |
Solving Constraint Satisfiability Problem for Automatic Generation of Design Verification Vectors
|
R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:42:21Z |
A False-Path Aware Formal Static Timing Analyzer Considering Simultaneous Input Transitions
|
Shih-Heng Tsai;Chung-Yang (Ric) Huang; Shih-Heng Tsai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:42:21Z |
Interpolant Generation without Constructing Resolution Graph
|
Chih-Jen Hsu;Shao-Lun Huang;Chia-An Wu;Chung-Yang (Ric) Huang; Chih-Jen Hsu; Shao-Lun Huang; Chia-An Wu; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:42:21Z |
Electronic Design Automation: Synthesis, Verification, and Test
|
L-T. Wang;K-T. Cheng;Y-W. Chang;C-Y. Huang;et. al.; L-T. Wang; K-T. Cheng; Y-W. Chang; C-Y. Huang; et. al.; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:08:52Z |
Libra - A Library-Independent Framework for Post-Layout Performance Optimization
|
R.C.-Y. Huang; Y. Wang; K.-T. Cheng; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:08:52Z |
A New Extended Finite State Machine (EFSM) Model for RTL Design Verification
|
R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:08:52Z |
Improving Constant-Coefficient Multiplier Verification by Partial Product Identification
|
Chao-Yue (Colby) Lai; Chung-Yang (Ric) Huang; Kei-Yong Khoo; CHUNG-YANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:08:52Z |
Speeding Up SoC Virtual Platform Simulation by Data-Dependency Aware Virtual Synchronization
|
Kuen-Huei Lin;Siao-Jie Cai;Chung-Yang (Ric) Huang; Kuen-Huei Lin; Siao-Jie Cai; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG |
