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Showing items 1-8 of 8 (1 Page(s) Totally)
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| 亞洲大學 |
2013-01 |
An Analytical Model of Triple RESURF Device with Linear P?layer Doping Profile
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Hua, Tingting;Hua, Tingting;Guo, Yufeng;Guo, Yufeng;Yu, Ying;Yu, Ying;許健;Sheu, Gene;Yao, Jiafei;Yao, Jiafei |
| 亞洲大學 |
2013-01 |
Novel Silicon-on-Insulator Lateral Power Device with Partial Oxide Pillars in the Drift Region
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Yao, JiaFei;Yao, JiaFei;Guo, Yufeng;Guo, Yufeng;Hua, Tingting;Hua, Tingting;Huang, Shi;Huang, Shi;Zh, Changchun;Zhang, Changchun;Xia, Xiaojuan;Xia, Xiaojuan;許健;Sheu, Gene |
| 亞洲大學 |
2009.07 |
VARIATION OF LATERAL THICKNESSTECHNIQUES IN SOI LATERAL HIGH VOLTAGE DEVICE
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郭宇鋒;Guo, Yufeng;王至剛;Wang1, Zhigong;許健;Sheu, Gene |
| 亞洲大學 |
2009-11 |
A three-dimensional breakdown model of SOI lateral power transistors with a circular layout
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Guo, Yufeng ; Wang, Zhigong ; Sheu, Gene |
| 亞洲大學 |
2009-11 |
A Three-dimensional Breakdown Model of SOI Lateral Power Transistors with a Circular Layout
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郭宇峰;Guo, Yufeng;Wang, Zhigong;許健;Sheu, Gene |
| 亞洲大學 |
2009-07 |
VARIATION OF LATERAL THICKNESSTECHNIQUES IN SOI LATERAL HIGH VOLTAGE DEVICE
|
郭宇鋒;Guo,Yufeng;王至剛;Wang1,Zhigong;許健;Sheu,Gene |
| 亞洲大學 |
2009-07 |
Variaton of Lateral Thickness techniques in SOI Lateral High Voltage Transistors
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郭宇鋒;Guo, Yufeng;王至剛;Wang, Zhigong;許健;Sheu, Gene |
| 亞洲大學 |
2009 |
Variation of lateral thickness techniques in sol lateral high voltage transistors
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Guo, Yufeng ; Wang, Zhigong ; Sheu, Gene |
Showing items 1-8 of 8 (1 Page(s) Totally)
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