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Showing items 116-127 of 127  (6 Page(s) Totally)
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Institution Date Title Author
國立臺灣科技大學 2015 Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs Lu, S.-K.;Lin, S.-L.;Lin, H.-W.;Hashizume, M.
國立臺灣科技大學 2015 Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit Nanbara, K.;Odoriba, A.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.
國立臺灣科技大學 2015 A testable design for electrical interconnect tests of 3D ICs Odoriba, A.;Umezu, S.;Hashizume, M.;Yotsuyanagi, H.;Ali, F.A.B.;Lu, S.-K.
國立臺灣科技大學 2015 An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories Lu, S.-K;Lin, H.-W;Hashizume, M.
國立臺灣科技大學 2015 Electrical interconnect test method of 3D ICs without boundary scan flip flops Hashizume, M;Umezu, S;Ikiri, Y;Ali, F.A.B;Yotsuyanagi, H;Lu, S.-K.
臺大學術典藏 2014 Effect of Asian dust storms on mortality in three Asian cities YUE-LIANG GUO; Lee, H. ; Honda, Y. ; Lim, Y.-H. ; Guo, Y.L. ; Hashizume, M. ; Kim, H.
國立臺灣科技大學 2013 Testable design for electrical testing of open defects at interconnects in 3D ICs Hashizume, M.;Konishi, T.;Yotsuyanag, H.;Lu, S.-K.
國立臺灣科技大學 2013 Reduction method of number of electromagnetic simulation times for estimating output voltage at hard open TSV in 3D IC Haraguchi, E.;Hashizume, M.;Manabe, K.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K.;Roth, Z.
國立臺灣科技大學 2013 Built-in IDDT appearance time sensor for detecting open faults in 3D IC Suenaga, S.;Hashizume, M.;Yotsuyanagi, H.;Tada, T.;Lu, S.-K.
國立臺灣科技大學 2013 Fault scrambling techniques for yield enhancement of embedded memories Lu, S.-K.;Jheng, H.-C.;Hashizume, M.;Huang, J.-L.;Ning, P.
國立臺灣科技大學 2013 DFT for supply current testing to detect open defects at interconnects in 3D ICs Suenaga, S.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K.;Roth, Z.
國立臺灣科技大學 2013 An efficient test and repair flow for yield enhancement of one-time-programming NROM-based ROMs Li, T.-L.;Hashizume, M.;Lu, S.-K.

Showing items 116-127 of 127  (6 Page(s) Totally)
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