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Showing items 91-115 of 127 (6 Page(s) Totally)
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| 國家衛生研究院 |
2018-07-31 |
Quantifying excess deaths related to heatwaves under climate change scenarios: A multicountry time series modelling study
|
Guo, Y;Gasparrini, A;Li, S;Sera, F;Vicedo-Cabrera, AM;de Sousa Zanotti Stagliorio Coelho, M;Saldiva, PHN;Lavigne, E;Tawatsupa, B;Punnasiri, K;Overcenco, A;Correa, PM;Ortega, NV;Kan, H;Osorio, S;Jaakkola, JJK;Ryti, NRI;Goodman, PG;Zeka, A;Michelozzi, P;Scortichini, M;Hashizume, M;Honda, Y;Seposo, X;Kim, H;Tobias, A;��iguez, C;Forsberg, B;�str�m, DO;Guo, YL;Chen, BY;Zanobetti, A;Schwartz, J;Dang, TN;Van, DD;Bell, ML;Armstrong, B;Ebi, KL;Tong, S |
| 國立臺灣科技大學 |
2018 |
A design for testability of open defects at interconnects in 3D stacked ICs
|
Ashikin F.; Hashizume M.; Yotsuyanagi H.; Lu S.-K.; Roth Z. |
| 國立臺灣科技大學 |
2018 |
Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories
|
Lu S.-K.; Jheng H.-C.; Lin H.-W.; Hashizume M. |
| 國立臺灣科技大學 |
2018 |
Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories
|
Lu S.-K.; Zhong S.-X.; Hashizume M. |
| 國立臺灣科技大學 |
2018 |
A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type
|
Kanda, M.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2018 |
A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume
|
Ohtani, K.;Osato, N.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2018 |
Open defect detection with a built-in test circuit by IDDT appearance time in CMOS ICs
|
Kambara A.; Yotsuyanagi H.; Miyoshi D.; Hashizume M.; Lu S.-K. |
| 國立臺灣科技大學 |
2018 |
Fault-aware page address remapping techniques for enhancing yield and reliability of flash memories
|
Lu S.-K.; Yu S.-C.; Hashizume M.; Yotsuyanagi H. |
| 國家衛生研究院 |
2017-08-10 |
Heat wave and mortality: A multicountry, multicommunity study
|
Guo, Y;Gasparrini, A;Armstrong, BG;Tawatsupa, B;Tobias, A;Lavigne, E;Coelho, M;Pan, X;Kim, H;Hashizume, M;Honda, Y;Guo, YL;Wu, CF;Zanobetti, A;Schwartz, JD;Bell, ML;Scortichini, M;Michelozzi, P;Punnasiri, K;Li, S;Tian, L;Garcia, SDO;Seposo, X;Overcenco, A;Zeka, A;Goodman, P;Dang, TN;Dung, DV;Mayvaneh, F;Saldiva, PHN;Williams, G;Tong, S |
| 國家衛生研究院 |
2017-05 |
Temporal changes in mortality related to extreme temperatures for 15 cities in northeast Asia: Adaptation to heat and maladaptation to cold
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Chung, Y;Noh, H;Honda, Y;Hashizume, M;Bell, ML;Guo, YLL;Kim, H |
| 國立臺灣科技大學 |
2017 |
Electrical tests for capacitive open defects in assembled PCBs
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Alia, F.A.B.;Odoriba, A.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2017 |
Electrical test of resistive and capacitive open defects at data bus in 3D memory IC
|
Hashizume, M.;Shiraishi, Y.;Yotsuyanagi, H.;Yokoyama, H.;Tada, Tada T.;Lu, S.-K. |
| 國立臺灣科技大學 |
2017 |
Resistive open defects detected by interconnect testing based on charge volume injected to 3D ICs
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Ohtani, K.;Osato, N.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2017 |
A built-in current sensor made of a comparator of offset cancellation type for electrical interconnect tests of 3D ICs
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Kanda, M.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories
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Lu, S.-K;Tsai, C.-J;Hashizume, M. |
| 國立臺灣科技大學 |
2016 |
A built-in electrical test circuit for detecting open leads in assembled PCB circuits
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Miyabe, T;Hashizume, M;Yotsuyanagi, H;Lu, S.-K;Roth, Z. |
| 國立臺灣科技大學 |
2016 |
Electrical interconnect test of solder joint part with boundary scan flip flops and a built-in test circuit
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Hashizume, M;Ikiri, Y;Konishi, T;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories
|
Lu, S.-K;Tsai, C.-J;Hashizume, M. |
| 國立臺灣科技大學 |
2016 |
A power supply circuit for interconnect tests based on injected charge volume of 3D IC
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Ohtani, K;Hashizume, M;Suga, D;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
A built-in defective level monitor of resistive open defects in 3D ICs with logic gates
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Hashizume, M;Odoriba, A;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
Testability for resistive open defects by electrical interconnect test of 3D ICs without boundary scan flip flops
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Ali, F.A.B;Hashizume, M;Ikiri, Y;Yotsuyanagi, H;Lu, S.-K. |
| 國立臺灣科技大學 |
2016 |
Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories
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Lu, S.-K;Zhong, S.-X;Hashizume, M. |
| 國立臺灣科技大學 |
2016 |
An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories
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Lu, S.-K;Lin, H.-W;Hashizume, M. |
| 國立臺灣科技大學 |
2015 |
Address scrambling and data inversion techniques for yield enhancement of NROM-Based ROMs
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Lu, S.-K.;Li, T.-L.;Hashizume, M.;Chen, J.-L. |
| 國立臺灣科技大學 |
2015 |
Electrical interconnect test method of 3D ICs by injected charge volume
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Suga, D.;Hashizume, M.;Yotsuyanagi, H.;Lu, S.-K. |
Showing items 91-115 of 127 (6 Page(s) Totally)
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