臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T05:27:05Z	A calibrated pulse generator for impulse-radio UWB applications	Che-Fu Liang; Shih-Tsai Liu; Hsiang-Hui Chang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T04:59:17Z	Low jitter and multi-rate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection	Hsiang-Hui Chang; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T04:35:30Z	A Shifted-Averaging VCO with Precise Multiphase Outputs and Low Jitter Operation	Hsiang-Hui Chang; Shang-Ping Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T04:35:29Z	A sub-1V fourth-order bandpass delta-sigma modulator	Hsiang-Hui Chang; Chien-Hung Kuo; Ming-Huang Liu; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T04:35:29Z	A Low Jitter and Precise Multiphase Delay-Locked Loop Using Shifted Averaging VCDL	Hsiang-Hui Chang; Chih-Hao Sun; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T04:35:28Z	An 800Mb/s tracking clock recovery receiver for the IEEE P1394a serial bus	Hsiang-Hui Chang; Giang-Kaai Dehng; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T04:35:28Z	A fast locking and low jitter delay-locked loop using DHDL	Hsiang-Hui Chang; Jyh-Woei Lin; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T04:15:15Z	A wide-range delay-locked loop with a fixed latency of one clock cycle	Hsiang-Hui Chang; Jyh-Woei Lin; Ching-Yuan Yang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T03:50:27Z	CMOS Magnetic to Digital Converter Using  Oversampling ModulatorCMOS Magnetic to Digital Converter Using  Oversampling Modulator	SHEN-IUAN LIU; Shr-Lung Chen; Hsiang-Hui Chang; Kun-Hsien Li; Shen-Iuan Liu
國立臺灣師範大學	2014-10-30T09:28:40Z	A Sub-1V Fourth-Bandpass Delta-Sigma Modulator	Hsiang-Hui Chang; Chien-Hung Kuo; Ming-Huang Liu; Shen-Iuan Liu

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