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Taiwan Academic Institutional Repository >
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"huang jiun lang"
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| 臺大學術典藏 |
2020-06-11T06:50:43Z |
A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays.
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Lin, Chen-Wei;Huang, Jiun-Lang; Lin, Chen-Wei; Huang, Jiun-Lang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:41Z |
Guest Editors' Introduction: A Promising Alternative to Conventional Silicon
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Huang, Jiun-Lang;Cheng, Kwang-Ting; Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:40Z |
An FPGA-Based Data Receiver for Digital IC Testing.
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Huang, Wei-Chen;Hou, Guan-Hao;Huang, Jiun-Lang;Kuo, Terry; Huang, Wei-Chen; Hou, Guan-Hao; Huang, Jiun-Lang; Kuo, Terry; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:38Z |
A robust ADC code hit counting technique.
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Huang, Jiun-Lang;Chou, Kuo-Yu;Lu, Ming-Huan;Huang, Xuan-Lun; Huang, Jiun-Lang; Chou, Kuo-Yu; Lu, Ming-Huan; Huang, Xuan-Lun; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T06:03:13Z |
A low-cost jitter measurement technique for BIST applications
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Huang, Jiun-Lang; J.-L. Huang; J.-J. Huang; Y.-S. Liu |
| 國立臺灣大學 |
2009 |
LPTest: A Flexible Low-Power Test Pattern Generator
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Wu, Meng-Fan; Hu, Kai-Shun; Huang, Jiun-Lang |
| 國立臺灣大學 |
2009 |
Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment
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Wu, Meng-Fan; Huang, Jiun-Lang; Wen, Xiaoqing; Miyase, K. |
| 國立臺灣大學 |
2009 |
A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays
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Lin, Chen-Wei; Huang, Jiun-Lang |
| 國立臺灣大學 |
2006 |
A low-cost jitter measurement technique for BIST applications
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Huang, Jiun-Lang; Huang, Jui-Jer; Liu, Yuan-Shuang |
| 國立臺灣大學 |
2006 |
On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines
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Huang, Jiun-Lang |
Showing items 1-10 of 16 (2 Page(s) Totally)
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