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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)
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Institution Date Title Author
國立交通大學 2017-04-21T06:49:29Z Stacked Low-Voltage PMOS for High-Voltage ESD Protection with Latchup-Free Immunity Tang, Kai-Neng; Liao, Seian-Feng; Ker, Ming-Dou; Chiou, Hwa-Chyi; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih
國立交通大學 2017-04-21T06:49:12Z ESD Protection Design with Latchup-Free Immunity in 120V SOI Process Huang, Yi-Jie; Ker, Ming-Dou; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih
國立交通大學 2017-04-21T06:49:05Z Impact of Guard Ring Layout on the Stacked Low-Voltage PMOS for High-Voltage ESD Protection Liao, Seian-Feng; Tang, Kai-Neng; Ker, Ming-Dou; Yeh, Jia-Rong; Chiou, Hwa-Chyi; Huang, Yeh-Jen; Tsai, Chun-Chien; Jou, Yeh-Ning; Lin, Geeng-Lih
國立交通大學 2014-12-16T06:15:12Z ELECTROSTATIC DISCHARGE PROTECTION DEVICE HUANG Yeh-Jen; Jou Yeh-Ning; Ker Ming-Dou; Chen Wen-Yi; Hung Chia-Wei; Chiou Hwa-Chyi
國立交通大學 2014-12-16T06:13:59Z Electrostatic discharge protection device Huang Yeh-Jen; Jou Yeh-Ning; Ker Ming-Dou; Chen Wen-Yi; Hung Chia-Wei; Chiou Hwa-Chyi
國立交通大學 2014-12-08T15:47:28Z Measurement on Snapback Holding Voltage of High-Voltage LDMOS for Latch-up Consideration Chen, Wen-Yi; Ker, Ming-Dou; Huang, Yeh-Jen; Jou, Yeh-Ning; Lin, Geeng-Lih
國立交通大學 2014-12-08T15:23:36Z Improvement on ESD Robustness of Lateral DMOS in High-Voltage CMOS ICs by Body Current Injection Chen, Wen-Yi; Ker, Ming-Dou; Jou, Yeh-Ning; Huang, Yeh-Jen; Lin, Geeng-Lih
國立交通大學 2014-12-08T15:11:16Z Investigation on the validity of holding voltage in high-voltage devices measured by transmission-line-pulsing (TLP) Chen, Wen-Yi; Ker, Ming-Dou; Huang, Yeh-Jen
義守大學 2009 Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection Chen, Wen-Yi ; Ker, Ming-Dou ; Jou, Yeh-Ning ; Huang, Yeh-Jen ; Lin, Geeng-Lih

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