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Institution Date Title Author
元智大學 May-22 A 12–14.5-GHz 10.2-mW −249-dB FoM Fractional-N Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS Yan-Ting Chen; Pen-Jui Peng; Hungwen Lin
元智大學 May-16 低電壓差動訊號模式發射與接收電路 邵致翔; 周世芳; Hungwen Lin
元智大學 Jun-18 LOW-VOLTAGE DIFFERENTIAL SIGNALING TRANSMITTER AND RECEIVER Hungwen Lin; Shih-Fang Jhou; Chih-Hsiang Shao
元智大學 Jun-18 LOW-VOLTAGE DIFFERENTIAL SIGNALING TRANSMITTER AND RECEIVER Hungwen Lin; Shih-Fang Jhou; Chih-Hsiang Shao
元智大學 Jun-18 LOW-VOLTAGE DIFFERENTIAL SIGNALING TRANSMITTER AND RECEIVER Hungwen Lin; Shih-Fang Jhou; Chih-Hsiang Shao
元智大學 Jun-18 LOW-VOLTAGE DIFFERENTIAL SIGNALING TRANSMITTER AND RECEIVER Hungwen Lin; Shihfang Jhoh; Chihhsiang Shao
元智大學 Aug-22 A 100-Gb/s PAM-4 Voltage-Mode Transmitter With High-Resolution Unsegmented Three-Tap FFE in 40-nm CMOS Yan-Ting Chen; Pen-Jui Peng; Hungwen Lin
元智大學 2023-07-17 A SSN reduction technique for single-ended I/O, parallel link system Hungwen Lin; Chung-Yen Lin; Tzu-Yu Teng; Chi-Ting Ke
元智大學 2022-07-06 A Low Process Sensitivity inverter-based RX Analog Front-End Design Tzu-Hao Lin; Hungwen Lin
元智大學 2021-09-15 A Buffer Circuit for the Interface of RF and Baseband System Zhi-Sheng Zhang; Zhi-Yi Chen; Hungwen Lin

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