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"hwang wei"的相關文件
顯示項目 51-60 / 202 (共21頁)
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| 國立交通大學 |
2015-07-21T11:20:58Z |
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist
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Lien, Nan-Chun; Chu, Li-Wei; Chen, Chien-Hen; Yang, Hao-I.; Tu, Ming-Hsien; Kan, Paul-Sen; Hu, Yong-Jyun; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei |
| 國立交通大學 |
2015-07-21T11:20:52Z |
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications
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Huang, Po-Tsang; Wu, Shang-Lin; Huang, Yu-Chieh; Chou, Lei-Chun; Huang, Teng-Chieh; Wang, Tang-Hsuan; Lin, Yu-Rou; Cheng, Chuan-An; Shen, Wen-Wei; Chuang, Ching-Te; Chen, Kuan-Neng; Chiou, Jin-Chern; Hwang, Wei; Tong, Ho-Ming |
| 國立交通大學 |
2015-07-21T08:31:30Z |
2.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural-Sensing Applications
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Huang, Po-Tsang; Chou, Lei-Chun; Huang, Teng-Chieh; Wu, Shang-Lin; Wang, Tang-Shuan; Lin, Yu-Rou; Cheng, Chuan-An; Shen, Wen-Wei; Chen, Kuan-Neng; Chiou, Jin-Chern; Chuang, Ching-Te; Hwang, Wei; Chen, Kuo-Hua; Chiu, Chi-Tsung; Cheng, Ming-Hsiang; Lin, Yueh-Lung; Tong, Ho-Ming |
| 國立交通大學 |
2015-07-21T08:31:17Z |
Energy-Efficient Configurable Discrete Wavelet Transform for Neural Sensing Applications
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Wang, Tang-Hsuan; Huang, Po-Tsang; Chen, Kuan-Neng; Chiou, Jin-Chem; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chuang, Ching-Te; Hwang, Wei |
| 國立交通大學 |
2015-07-21T08:31:00Z |
A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control
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Liao, Wei-Nan; Lien, Nan-Chun; Chang, Chi-Shin; Chu, Li-Wei; Yang, Hao-I; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; Tu, Ming-Hsien; Huang, Huan-Shun; Wang, Jian-Hao; Kan, Paul-Sen; Hu, Yong-Jyun |
| 國立交通大學 |
2015-07-21T08:31:00Z |
A DUAL-EDGED TRIGGERED EXPLICIT-PULSED LEVEL CONVERTING FLIP-FLOP WITH A WIDE OPERATION RANGE
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Chen, Mei-Wei; Chang, Ming-Hung; Wu, Pei-Chen; Kuo, Yi-Ping; Yang, Chun-Lin; Chu, Yuan-Hua; Hwang, Wei |
| 國立交通大學 |
2015-07-21T08:29:00Z |
A double-sided, single-chip integration scheme using through-silicon-via for neural sensing applications
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Chang, Chih-Wei; Chou, Lei-Chun; Huang, Po-Tsang; Wu, Shang-Lin; Lee, Shih-Wei; Chuang, Ching-Te; Chen, Kuan-Neng; Hwang, Wei; Chen, Kuo-Hua; Chiu, Chi-Tsung; Tong, Ho-Ming; Chiou, Jin-Chern |
| 國立交通大學 |
2014-12-16T06:16:13Z |
Power gating structure having data retention and intermediate modes
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Hua, Chung-Hsien; Hwang, Wei |
| 國立交通大學 |
2014-12-16T06:16:06Z |
XOR-based conditional keeper and an architecture implementing its application to match lines
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Hua, Chung-Hsien; Peng, Chi-Wei; Hwang, Wei |
| 國立交通大學 |
2014-12-16T06:16:06Z |
Asynchronous first-in first-out cell
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Chu, Yeh-Lin; Hwang, Wei |
顯示項目 51-60 / 202 (共21頁)
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