臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T08:18:16Z	A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression	Chao-Ching Hung;I-Fong Chen;Shen-Iuan Liu; Chao-Ching Hung; I-Fong Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T08:18:16Z	A 1.25GHz fast-locked all-digital phase-locked loop with supply noise suppression	Chao-Ching Hung;I-Fong Chen;Shen-Iuan Liu; Chao-Ching Hung; I-Fong Chen; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:01Z	Loop latency reduction technique for all-digital clock and data recovery circuits	I-Fong Chen;Rong-Jyi Yang;Shen-Iuan Liu; I-Fong Chen; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU
臺大學術典藏	2018-09-10T07:42:01Z	Loop latency reduction technique for all-digital clock and data recovery circuits	I-Fong Chen;Rong-Jyi Yang;Shen-Iuan Liu; I-Fong Chen; Rong-Jyi Yang; Shen-Iuan Liu; SHEN-IUAN LIU

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