臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Showing items 31-40 of 176 (18 Page(s) Totally)
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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T09:50:25Z	Novel Power Consumption Reduction strategy Using Mixed-Vth Cells for Optimizaing the Cells on Critical Paths for Low-Power SOC	G. Lin;J. B. Kuo; G. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T09:50:25Z	Novel Power Consumption Reduction strategy Using Mixed-Vth Cells for Optimizaing the Cells on Critical Paths for Low-Power SOC	G. Lin;J. B. Kuo; G. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T09:50:25Z	Turn-off Transient Behavior of PD SOI NMOS Device Considering the Back-Gate Bias Effect	D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO; D. H. Lung;J. B. Kuo;D. Chen
臺大學術典藏	2018-09-10T09:50:25Z	Turn-off Transient Behavior of PD SOI NMOS Device Considering the Back-Gate Bias Effect	D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO; D. H. Lung;J. B. Kuo;D. Chen
臺大學術典藏	2018-09-10T09:50:25Z	Modeling Advanced PD SOI CMOS Devices	J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T09:50:25Z	Modeling Advanced PD SOI CMOS Devices	J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T09:50:25Z	Back-Gate Bias Effect of PD SOI NMOS Device Considering BJT	D. H. Lung;J. B. Kuo; D. H. Lung; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T09:50:25Z	Back-Gate Bias Effect of PD SOI NMOS Device Considering BJT	D. H. Lung;J. B. Kuo; D. H. Lung; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T09:50:25Z	Analytical Drain Current Model for Poly-Si Thin-Film Transistors Biased in Strong Inversion Considering Degradation of Tail States at Grain Boundary	L. L. Wang;J. B. Kuo;S. Zhang; L. L. Wang; J. B. Kuo; S. Zhang; JAMES-B KUO
臺大學術典藏	2018-09-10T09:50:25Z	Analytical Drain Current Model for Poly-Si Thin-Film Transistors Biased in Strong Inversion Considering Degradation of Tail States at Grain Boundary	L. L. Wang;J. B. Kuo;S. Zhang; L. L. Wang; J. B. Kuo; S. Zhang; JAMES-B KUO

Showing items 31-40 of 176 (18 Page(s) Totally)
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