臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	Repositories
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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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	臺大學術典藏NTU Scholars

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit	C. B. Hsu;Y. S. Hong;J. B. Kuo; C. B. Hsu; Y. S. Hong; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit	C. B. Hsu;Y. S. Hong;J. B. Kuo; C. B. Hsu; Y. S. Hong; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS Low-Power Design Technique (LPDT) for Low-Voltage Piepelined Mcoprocessor Circuit	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS Low-Power Design Technique (LPDT) for Low-Voltage Piepelined Mcoprocessor Circuit	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	Parasitic BJT versus DIBL: Floating-Body-Related Subthreshold Characteristics of SOI NMOS Device	D. H. Lung;S. K. Hu;J. B. Kuo;D. Chen; D. H. Lung; S. K. Hu; J. B. Kuo; D. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	Parasitic BJT versus DIBL: Floating-Body-Related Subthreshold Characteristics of SOI NMOS Device	D. H. Lung;S. K. Hu;J. B. Kuo;D. Chen; D. H. Lung; S. K. Hu; J. B. Kuo; D. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	A Surface-Field-Based Model for Nanowire MOSFETs with Spatial Variations of Doping Profiles	Q. Cheng;C. Y. Hong;J. B. Kuo;Y. J. Chen; Q. Cheng; C. Y. Hong; J. B. Kuo; Y. J. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	A Surface-Field-Based Model for Nanowire MOSFETs with Spatial Variations of Doping Profiles	Q. Cheng;C. Y. Hong;J. B. Kuo;Y. J. Chen; Q. Cheng; C. Y. Hong; J. B. Kuo; Y. J. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Subthreshold Behavior of the SOI NMOS Device Consdiering BJT and DIBL Effects	D. H. Lung;J. B. Kuo; D. H. Lung; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Subthreshold Behavior of the SOI NMOS Device Consdiering BJT and DIBL Effects	D. H. Lung;J. B. Kuo; D. H. Lung; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC	G. Lin;C. B. Hsu;J. B. Kuo; G. Lin; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC	G. Lin;C. B. Hsu;J. B. Kuo; G. Lin; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs	JAMES-B KUO; J. B. Kuo; G. Lin; G. Lin;J. B. Kuo
臺大學術典藏	2018-09-10T15:00:17Z	Critical-path aware power consumption optimization methodology (CAPCOM) using mixed-VTH cells for low-power SOC designs	JAMES-B KUO; J. B. Kuo; G. Lin; G. Lin;J. B. Kuo
臺大學術典藏	2018-09-10T15:00:17Z	Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Back-Gate-Baias Induced Floating-Body-Related Subthreshold Characteristics of SOI NMOS Device	S. K. Hu;D. H. Lung;J. B. Kuo;D. Chen; S. K. Hu; D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:17Z	Back-Gate-Baias Induced Floating-Body-Related Subthreshold Characteristics of SOI NMOS Device	S. K. Hu;D. H. Lung;J. B. Kuo;D. Chen; S. K. Hu; D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T09:50:25Z	Function of the Upper/Lower Parasitic BJTs in 40nm PD SOI NMOS Device due to the Back-Gate Bias Effect	A. P. Chuang;S. I. Su;Z. H. Yang;J. B. Kuo;D. Chen;C. S. Yeh; A. P. Chuang; S. I. Su; Z. H. Yang; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏	2018-09-10T09:50:25Z	Function of the Upper/Lower Parasitic BJTs in 40nm PD SOI NMOS Device due to the Back-Gate Bias Effect	A. P. Chuang;S. I. Su;Z. H. Yang;J. B. Kuo;D. Chen;C. S. Yeh; A. P. Chuang; S. I. Su; Z. H. Yang; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
臺大學術典藏	2018-09-10T09:50:25Z	Novel Power Consumption Reduction strategy Using Mixed-Vth Cells for Optimizaing the Cells on Critical Paths for Low-Power SOC	G. Lin;J. B. Kuo; G. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T09:50:25Z	Novel Power Consumption Reduction strategy Using Mixed-Vth Cells for Optimizaing the Cells on Critical Paths for Low-Power SOC	G. Lin;J. B. Kuo; G. Lin; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T09:50:25Z	Turn-off Transient Behavior of PD SOI NMOS Device Considering the Back-Gate Bias Effect	D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO; D. H. Lung;J. B. Kuo;D. Chen
臺大學術典藏	2018-09-10T09:50:25Z	Turn-off Transient Behavior of PD SOI NMOS Device Considering the Back-Gate Bias Effect	D. H. Lung; J. B. Kuo; D. Chen; JAMES-B KUO; D. H. Lung;J. B. Kuo;D. Chen
臺大學術典藏	2018-09-10T09:50:25Z	Modeling Advanced PD SOI CMOS Devices	J. B. Kuo; J. B. Kuo; JAMES-B KUO

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