| 臺大學術典藏 |
2018-09-10T06:35:00Z |
STI Mechanical Stress Induced Subthreshold Kink Effect of 40nm PD SOI NMOS Devices
|
J. B. kuo; M. Ma; C. T. Tsai; C. S. Yeh; D. Chen; JAMES-B KUO; I. Lin; V. Su |
| 臺大學術典藏 |
2018-09-10T06:34:59Z |
Narrow Band Gap Semiconductor
|
H. H. Lin; J. B. Kuo; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T06:34:59Z |
Triple-Threshold Static Power Minimization Technique in High-Level Synthesis for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology
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H. I. Chen;E. K. Loo;J. B. Kuo;M. J. Syrzycki; H. I. Chen; E. K. Loo; J. B. Kuo; M. J. Syrzycki; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T06:34:59Z |
Triple-Threshold Static Power Minimization Technique in High-Level Synthesis for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology
|
H. I. Chen;E. K. Loo;J. B. Kuo;M. J. Syrzycki; H. I. Chen; E. K. Loo; J. B. Kuo; M. J. Syrzycki; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T06:02:16Z |
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique
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B. Chung; J. B. Kuo; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T06:02:16Z |
Analysis of Fringing Electric Field Related Capacitance Behavior of Narrow-Channel FD SOI NMOS Devices Using 3D Simulation
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C. C. Chen; J. B. Kuo; K. W. Su; S. Liu; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T06:02:15Z |
Partitioned gate tunnelling current model considering distributed effect for CMOS devices with ultra-thin (1 nm) gate oxide
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C. H. Lin; J. B. KUO; K. W. Su; S. Liu; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T06:02:15Z |
Gate capacitances behavior of nanometer FD SOI CMOS devices with HfO2 high-k gate dielectric considering vertical and fringing displacement effects using 2-D simulation
|
Y. S. Lin; C. H. Lin; J. B. Kuo; K. W. Su; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T06:02:15Z |
Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOINMOS device considering the 3-D fringing capacitances using 3-D simulation
|
C. C. Chen; J. B. Kuo; K. W. Su,; S. Liu; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T06:02:15Z |
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology
|
B. Chung; J. B. Kuo; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T06:02:15Z |
Fringing Effects of Nanometer SOI CMOS Devices
|
J. B. Kuo; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T05:26:48Z |
Fringing-Induced Narrow-Channel-Effect (FINCE) RElated Capacitance Behavior of Nanometer FD SOI NMOS Devices Using Mesa-Isolation Via 3D Simulation
|
G. S. Lin; J. B. Kuo; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T05:26:48Z |
CGS Capacitance Phenomenon of 100nm FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Vertical and Fringing Displacement Effects
|
Y. S. Lin; C. H. Lin; J. B. Kuo; K. W. Su; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T04:59:04Z |
Gate Misalignment Effect Related Capacitance Behavior of a 100nm DG FD SOI NMOS Device with n+/p+ Poly Top/Bottom Gate
|
C. H. Hsu; C. P. Yang; JAMES-B KUO; J. B. Kuo |
| 臺大學術典藏 |
2018-09-10T04:59:04Z |
Low-Voltage SOI CMOS VLSI Devices and Circuits
|
J. B. Kuo; S. C. Lin; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T04:59:03Z |
A Compact Threshold Voltage Model for Gate Misalignment Effect of DG FD SOI NMOS Devices Considering Fringing Electric Field Effects
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E. C. Sun; J. B. Kuo; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T04:59:03Z |
PD SOI-Technology SPICE Models
|
J. B. Kuo; S. C. Lin; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T04:59:03Z |
A Low-Voltage CMOS Load Driver with the Adiabatic and Bootstrap Techniques for Low-Power System Applications
|
J. B. Kuo;H. P. Chen; J. B. Kuo; H. P. Chen; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T04:59:03Z |
A Low-Voltage CMOS Load Driver with the Adiabatic and Bootstrap Techniques for Low-Power System Applications
|
J. B. Kuo;H. P. Chen; J. B. Kuo; H. P. Chen; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T04:59:03Z |
Trends on CMOS VLSI
|
J. B. Kuo; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T04:35:19Z |
Compact Modeling of SOI CMOS VLSI Devices
|
J. .B. Kuo; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T04:35:19Z |
Asymmetric Gate Misalignment Effect on Subthreshold Characteristics DG SOI NMOS Devices Considering Fringing Electric Field Effect
|
M. T. Lin; E. C. Sun; J. B. Kuo; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T04:35:18Z |
Ultra-low-voltage SOI CMOS Inverting Driver Circuit Using Effective Charge Pump Based on Bootstrap Technique
|
JAMES-B KUO; J. B. Kuo; J. H. T. Chen |
| 臺大學術典藏 |
2018-09-10T04:35:18Z |
Modeling the Fringing Electric Field Effect on the Threshold Voltage of FD SOI NMOS Devices with the LDD/Sidewall Oxide Spacer Structure
|
S. C. Lin; J. B. Kuo; JAMES-B KUO |
| 臺大學術典藏 |
2018-09-10T04:35:18Z |
SOI CMOS VLSI
|
J. B. Kuo; JAMES-B KUO |
