臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T15:25:58Z	Floating-body-correlated subthreshold behavior of SOI NMOS device considering back-gate-bias effect	S. K. Hu;J. B. Kuo;Y. J. Chen; S. K. Hu; J. B. Kuo; Y. J. Chen; JAMES-B KUO
臺大學術典藏	2018-09-10T15:25:58Z	Analysis of Subthreshold Behavior of SOI NMOS De ice Considering Back-Gate-Bias-Related Flaoting Body Effect	S. K. Hu;J. B. Kuo; S. K. Hu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:25:58Z	Analysis of Subthreshold Behavior of SOI NMOS De ice Considering Back-Gate-Bias-Related Flaoting Body Effect	S. K. Hu;J. B. Kuo; S. K. Hu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	Compact Modeling of 40nm Pd SOI NMOS Devices Considering Floating Body Effect	J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	Compact Modeling of 40nm Pd SOI NMOS Devices Considering Floating Body Effect	J. B. Kuo; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit	C. B. Hsu;Y. S. Hong;J. B. Kuo; C. B. Hsu; Y. S. Hong; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit	C. B. Hsu;Y. S. Hong;J. B. Kuo; C. B. Hsu; Y. S. Hong; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS Low-Power Design Technique (LPDT) for Low-Voltage Piepelined Mcoprocessor Circuit	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	MTCMOS Low-Power Design Technique (LPDT) for Low-Voltage Piepelined Mcoprocessor Circuit	C. B. Hsu;J. B. Kuo; C. B. Hsu; J. B. Kuo; JAMES-B KUO
臺大學術典藏	2018-09-10T15:00:18Z	Parasitic BJT versus DIBL: Floating-Body-Related Subthreshold Characteristics of SOI NMOS Device	D. H. Lung;S. K. Hu;J. B. Kuo;D. Chen; D. H. Lung; S. K. Hu; J. B. Kuo; D. Chen; JAMES-B KUO

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