臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	Repositories
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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T08:18:40Z	Signal/Power integrity modeling of high-speed memory modules using chip-package-board co-analysis	W.-D. Guo; Y.-H. Lin; H.-S. Chen; Y-C Lu; J. Hong; C.-H. Yu; A. Cheng; J. Chou; C.-J. Chang; J. Ku; T.-L. Wu; R.-B. Wu; H.-H. Chuang; YI-CHANG LU; TZONG-LIN WU; HSIN-SHU CHEN; RUEY-BEEI WU et al.
臺大學術典藏	2018-09-10T08:18:39Z	A broadband chip-level power-bus model feasible for power integrity chip-package co-design in high-speed memory circuits	H.-H. Chuang;C.-J. Hsu;J. Hong;C.-H. Yu;A. Cheng;J. Ku;T.-L. Wu; H.-H. Chuang; C.-J. Hsu; J. Hong; C.-H. Yu; A. Cheng; J. Ku; T.-L. Wu; TZONG-LIN WU
臺大學術典藏	2018-09-10T08:18:39Z	A broadband chip-level power-bus model feasible for power integrity chip-package co-design in high-speed memory circuits	H.-H. Chuang;C.-J. Hsu;J. Hong;C.-H. Yu;A. Cheng;J. Ku;T.-L. Wu; H.-H. Chuang; C.-J. Hsu; J. Hong; C.-H. Yu; A. Cheng; J. Ku; T.-L. Wu; TZONG-LIN WU

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