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機構	日期	題名	作者
臺大學術典藏	2018-09-10T08:19:07Z	A scalable quantitative measure of IR-drop for scan pattern generation	M.-F. Wu;K.-H. Tsai;W.-T. Cheng;H.-C. Pan;J.-L. Huang;A. Kifli; M.-F. Wu; K.-H. Tsai; W.-T. Cheng; H.-C. Pan; J.-L. Huang; A. Kifli; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:19:07Z	Power supply noise reduction in broadcast-based compression environment for at-speed scan testing	C.-Y. Liang;M.-F. Wu;J.-L. Huang; C.-Y. Liang; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:19:06Z	An Improved Weight Assignment Scheme for IR-Drop-Aware At-Speed Scan Pattern Generation	M.-F. Wu;H.-C. Pan;T.-H. Wang;J.-L. Huang;K.-H. Tsai;W.-T. Cheng; M.-F. Wu; H.-C. Pan; T.-H. Wang; J.-L. Huang; K.-H. Tsai; W.-T. Cheng; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:19:06Z	A robust ADC code hit counting technique	J.-L. Huang;Kuo-Yu Chou;Ming-Huan Lu;Xuan-Lun Huang; J.-L. Huang; Kuo-Yu Chou; Ming-Huan Lu; Xuan-Lun Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T08:19:06Z	3D-PIC: An Error Tolerant 3D CMOS Imager	H.-M. Sherman Chang;J.-L. Huang;D.-M. Kwai;K.-T. Tim Cheng;C.-W. Wu; H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:04Z	A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition Method	K.-W. Yeh;M.-F. Wu;J.-L. Huang; K.-W. Yeh; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:04Z	A Self-Testing Assisted Pipelined-ADC Calibration Technique	J.-L. Huang;X.-L. Huang;P.-Y. Kang; J.-L. Huang; X.-L. Huang; P.-Y. Kang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:04Z	An On-Chip Integrator Leakage Characterization Technique and Its Applications to Switched Capacitor Circuits Testing	C.-Y. Yang;X.-L. Huang;J.-L. Huang; C.-Y. Yang; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	A DfT Technique for Diagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC Input	X.-L. Huang;C.-Y. Yang;J.-L. Huang; X.-L. Huang; C.-Y. Yang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment	M.-F. Wu;J.-L. Huang;X. Wen;K. Miyase; M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	LPTest: A Flexible Low-Power Test Pattern Generator	M.-F. Wu;K.-S. Hu;J.-L. Huang; M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	Specification back-propagation and its application to fault simulation of analog/mixed-signal circuits	J. L. Huang; C. Y. Pan; K. T. (Tim) Cheng; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	Characterizing Integrator Leakage of Single-Bit DS Modulator Using DC Input	X.-L. Huang;Y.-C. Yu;J.-L. Huang; X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:02Z	Ch. 8 Logic and Circuit Simulation	J.-L. Huang;C.-K. Koh;S. F. Cauley; J.-L. Huang; C.-K. Koh; S. F. Cauley; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:28Z	Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Testing	M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:28Z	Testing LCD Source Driver IC with Built-On-Scribe-Line Test Circuitry	J.-J. Huang;J.-L. Huang; J.-J. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:28Z	PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Testing in Huffman Coding Test Compression Environment	Y.-T. Lin;M.-F. Wu;J.-L. Huang; Y.-T. Lin; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:28Z	A Segmented a-Si Gate Driver Design for Power Reduction and Floating Gate Line Stabilization	P.-H. Chiu;J.-L. Huang; P.-H. Chiu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:27Z	A Self-Testing and Calibration Technique for Current-Steering DACs	Y.-L. Ma; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:27Z	Design of a Fault Tolerant Carry Lookahead Adder	C.-Y. Huang, T.-H. Ko; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:37:50Z	A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing	T.-L. Hung; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:37:50Z	An Efficient Peak Power Reduction Technique for Scan Testing	M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	A routability constrained scan chain ordering technique for test power reduction	X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	A period tracking based on-chip sinusoidal jitter extraction technique	C.-Y. Kuo; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance Testing	S.-W. Chang; J.-L. Huang; JIUN-LANG HUANG

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