臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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	臺大學術典藏NTU Scholars

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T07:43:03Z	LPTest: A Flexible Low-Power Test Pattern Generator	M.-F. Wu;K.-S. Hu;J.-L. Huang; M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	Specification back-propagation and its application to fault simulation of analog/mixed-signal circuits	J. L. Huang; C. Y. Pan; K. T. (Tim) Cheng; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:03Z	Characterizing Integrator Leakage of Single-Bit DS Modulator Using DC Input	X.-L. Huang;Y.-C. Yu;J.-L. Huang; X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:43:02Z	Ch. 8 Logic and Circuit Simulation	J.-L. Huang;C.-K. Koh;S. F. Cauley; J.-L. Huang; C.-K. Koh; S. F. Cauley; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:28Z	Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Testing	M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:28Z	Testing LCD Source Driver IC with Built-On-Scribe-Line Test Circuitry	J.-J. Huang;J.-L. Huang; J.-J. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:28Z	PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Testing in Huffman Coding Test Compression Environment	Y.-T. Lin;M.-F. Wu;J.-L. Huang; Y.-T. Lin; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:28Z	A Segmented a-Si Gate Driver Design for Power Reduction and Floating Gate Line Stabilization	P.-H. Chiu;J.-L. Huang; P.-H. Chiu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:27Z	A Self-Testing and Calibration Technique for Current-Steering DACs	Y.-L. Ma; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:27Z	Design of a Fault Tolerant Carry Lookahead Adder	C.-Y. Huang, T.-H. Ko; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:37:50Z	A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing	T.-L. Hung; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:37:50Z	An Efficient Peak Power Reduction Technique for Scan Testing	M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	A routability constrained scan chain ordering technique for test power reduction	X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	A period tracking based on-chip sinusoidal jitter extraction technique	C.-Y. Kuo; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance Testing	S.-W. Chang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter	J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:13Z	A low-cost jitter measurement technique for BIST applications	Huang, Jiun-Lang; J.-L. Huang; J.-J. Huang; Y.-S. Liu
臺大學術典藏	2018-09-10T06:03:13Z	On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines	J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T05:29:18Z	A Fabrication Process Variation Based Approach to Evaluate Design-for-Test Techniques	Y. R. Chen; J. L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T05:29:18Z	An On-Chip Random Jitter Testing Technique Using Low Tap-Count Delay Lines	J. L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T05:29:18Z	Random jitter testing using low tap-count delay lines	J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T04:59:50Z	An Infrastructure IP for On-Chip Clock Jitter Measurement	J. J. Huang; J. L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T04:36:02Z	A Delay-Line Based On-Chip Jitter Measurement Technique	J. J. Huang; J. L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T04:36:02Z	A Low-Cost Jitter Measurement Technique for BIST Applications	J. J. Huang; J. L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T04:15:41Z	Testing Second-Order Delta-Sigma Modulators using Pseudo-Random Patterns	C. K. Ong; J. L. Huang; K. T. Cheng; JIUN-LANG HUANG

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