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Showing items 1-8 of 8 (1 Page(s) Totally)
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| 臺大學術典藏 |
2020-06-16T06:38:46Z |
An Efficient and Simple VLSI Tree Architecture for Motion Estimation Algorithms
|
Jehng, Y.-S.;Chen, L.-G.;Chiueh, T.-D.; Jehng, Y.-S.; Chen, L.-G.; Chiueh, T.-D.; TZI-DAR CHIUEH |
| 臺大學術典藏 |
2018-09-10T05:15:51Z |
Pipeline interleaving design for FIR, IIR, and FFT array processors
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Chen, L.-G.;Jehng, Y.-S.;Chiueh, T.-D.; Chen, L.-G.; Jehng, Y.-S.; Chiueh, T.-D.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T05:15:51Z |
Pipeline interleaving design for FIR, IIR, and FFT array processors
|
Chen, L.-G.;Jehng, Y.-S.;Chiueh, T.-D.; Chen, L.-G.; Jehng, Y.-S.; Chiueh, T.-D.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:49Z |
An Efficient and Simple VLSI Tree Architecture for Motion Estimation Algorithms
|
Jehng, Y.-S.;Chen, L.-G.;Chiueh, T.-D.; Jehng, Y.-S.; Chen, L.-G.; Chiueh, T.-D.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:27:49Z |
An Efficient and Simple VLSI Tree Architecture for Motion Estimation Algorithms
|
Jehng, Y.-S.;Chen, L.-G.;Chiueh, T.-D.; Jehng, Y.-S.; Chen, L.-G.; Chiueh, T.-D.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T04:07:55Z |
Design and analysis of VLSI-based arithmetic arrays with error correction
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Chen, T.-H.; Chen, L.-G.; Jehng, Y.-S.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T03:43:47Z |
ASG: Automatic schematic generator
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Jehng, Y.-S.; Chen, L.-G.; Parng, T.-M.; LIANG-GEE CHEN |
| 臺大學術典藏 |
2018-09-10T03:43:47Z |
An Efficient Parallel Motion Estimation Algorithm Image Processing for Digital
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Chen, L.-G.; Chen, W.-T.; Jehng, Y.-S.; Chiueh, T.-D.; LIANG-GEE CHEN |
Showing items 1-8 of 8 (1 Page(s) Totally)
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