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Showing items 26-50 of 106  (5 Page(s) Totally)
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Institution Date Title Author
國立交通大學 2014-12-08T15:41:14Z High-speed and low-power split-radix FFT Yeh, WC; Jen, CW
國立交通大學 2014-12-08T15:41:10Z Motion estimation using MSD-first processing Su, CL; Jen, CW
國立交通大學 2014-12-08T15:40:17Z Generalized earliest-first fast addition algorithm Yeh, WC; Jen, CW
國立交通大學 2014-12-08T15:40:10Z MSD-first on-line arithmetic progressive processing implementation for motion estimation Su, CL; Jen, CW
國立交通大學 2014-12-08T15:39:41Z Optimal frame memory and data transfer scheme for MPEG-4 shape coding Lee, KB; Chin, HY; Chang, NYC; Hsu, HC; Jen, CW
國立交通大學 2014-12-08T15:35:06Z A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding Lee, KB; Lin, JY; Jen, CW
國立交通大學 2014-12-08T15:27:57Z A NOVEL MEMORY ARCHITECTURE FOR VIDEO SIGNAL PROCESSOR HUNG, JS; LIN, CH; JEN, CW
國立交通大學 2014-12-08T15:27:49Z A hardware-efficient architecture for 3-D graphics processor Liang, BS; Nieh, YC; Niou, YP; Jen, CW; Chuang, G
國立交通大學 2014-12-08T15:27:49Z HARDWARE SHARING IN TREE-STRUCTURE QMF BANKS LEE, HR; JEN, CW
國立交通大學 2014-12-08T15:27:49Z A RASTER ENGINE FOR COMPUTER GRAPHICS AND IMAGE COMPOSITION CHEN, CL; LIN, CH; LEE, HR; JEN, CW
國立交通大學 2014-12-08T15:27:38Z The IC design of a high speed RSA processor Yang, CC; Jen, CW; Chang, TS
國立交通大學 2014-12-08T15:27:37Z The IDCT processor on the Adder-Based distributed arithmetic Chen, CS; Chang, TS; Jen, CW
國立交通大學 2014-12-08T15:27:33Z A programmable concurrent video signal processor Chen, CC; Jen, CW
國立交通大學 2014-12-08T15:27:27Z An area and time efficient adder for multiple additions with different word-length Liang, BS; Nieh, YC; Jen, CW
國立交通大學 2014-12-08T15:27:23Z A novel recursive digital filter based on signed digit distributed arithmetic Su, CL; Hwang, YT; Jen, CW
國立交通大學 2014-12-08T15:27:17Z Hardware efficient transform designs with cyclic formulation and subexpression sharing Chang, TS; Jen, CW
國立交通大學 2014-12-08T15:27:14Z Low power FIR filter realization with differential coefficients and input Chang, TS; Jen, CW
國立交通大學 2014-12-08T15:27:14Z An architecture of full-search block matching for minimum memory bandwidth requirement Tuan, JC; Jen, CW
國立交通大學 2014-12-08T15:27:06Z Data stream generation for concurrent computation in VLSI signal processors Lin, TJ; Jen, CW
國立交通大學 2014-12-08T15:27:04Z A new hardware design and FPGA implementation for Internet routing towards IP over WDM and terabit routers Hsiao, IYL; Jen, CW
國立交通大學 2014-12-08T15:27:04Z Motion estimation using on-line arithmetic Su, CL; Jen, CW
國立交通大學 2014-12-08T15:27:03Z A high performance carry-save to signed-digit recoder for fused addition-multiplication Yeh, WC; Jen, CW
國立交通大學 2014-12-08T15:27:03Z On the study of logarithmic time parallel adders Yeh, WC; Jen, CW
國立交通大學 2014-12-08T15:26:37Z Cascade-configurable and scalable DSP environment Lin, TJ; Jen, CW
國立交通大學 2014-12-08T15:26:36Z Design and implementation of a scalable fast Fourier transform core Sung, CH; Lee, KB; Jen, CW

Showing items 26-50 of 106  (5 Page(s) Totally)
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