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"jen cw"的相关文件
显示项目 76-100 / 106 (共5页)
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| 國立交通大學 |
2014-12-08T15:17:31Z |
A compact DSP core with static floating-point arithmetic
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Lin, TJ; Lin, HY; Chao, CM; Liu, CW; Jen, CW |
| 國立交通大學 |
2014-12-08T15:06:26Z |
DEPLETION WIDTHS OF THE METAL-INSULATOR SEMICONDUCTOR (MIS) STRUCTURE
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JEN, CW; LEE, CL; LEI, TF |
| 國立交通大學 |
2014-12-08T15:06:09Z |
MOTA - A MOSFET TIMING SIMULATOR
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JOU, SJ; JEN, CW; SHEN, WZ; LEE, CL |
| 國立交通大學 |
2014-12-08T15:06:03Z |
ELLIPSOMETRY MEASUREMENTS ON SIO2-FILMS FOR THICKNESSES UNDER 200-A
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HO, JH; LEE, CL; JEN, CW; LEI, TF |
| 國立交通大學 |
2014-12-08T15:06:02Z |
SIMULATABLE TIMING MODEL FOR MOS LOGIC-CIRCUIT
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JOU, SJ; SHEN, WZ; JEN, CW; LEE, CL |
| 國立交通大學 |
2014-12-08T15:05:56Z |
DESIGN OF A SYSTOLIC ARRAY SYSTEM FOR LINEAR STATE-EQUATIONS
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JOU, SJ; JEN, CW |
| 國立交通大學 |
2014-12-08T15:05:45Z |
DESIGN OF ALGORITHM-BASED FAULT-TOLERANT VLSI ARRAY PROCESSOR
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LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:05:43Z |
MULTI-DIMENSIONAL PARALLEL COMPUTING STRUCTURES FOR REGULAR ITERATIVE ALGORITHMS
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JEN, CW; KWAI, DM |
| 國立交通大學 |
2014-12-08T15:05:35Z |
REDUNDANCY DESIGN FOR A FAULT TOLERANT SYSTOLIC ARRAY
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WANG, JJ; JEN, CW |
| 國立交通大學 |
2014-12-08T15:05:33Z |
DESIGN OF ONE-DIMENSIONAL SYSTOLIC-ARRAY SYSTEMS FOR LINEAR STATE-EQUATIONS
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JEN, CW; JOU, SJ |
| 國立交通大學 |
2014-12-08T15:05:01Z |
BIT-SLICED MEDIAN FILTER DESIGN BASED ON MAJORITY GATE
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LEE, CL; JEN, CW |
| 國立交通大學 |
2014-12-08T15:05:00Z |
DATA FLOW REPRESENTATION OF ITERATIVE ALGORITHMS FOR SYSTOLIC ARRAYS
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JEN, CW; KWAI, DM |
| 國立交通大學 |
2014-12-08T15:04:50Z |
ON THE DESIGN OF VLSI ARRAYS FOR DISCRETE FOURIER-TRANSFORM
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LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:04:46Z |
THE EFFICIENT MEMORY-BASED VLSI ARRAY DESIGNS FOR DFT AND DCT
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GUO, JI; LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:04:44Z |
A PARALLEL ADAPTIVE ALGORITHM FOR MOVING TARGET DETECTION AND ITS VLSI ARRAY REALIZATION
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LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:04:40Z |
A NEW ARRAY ARCHITECTURE FOR PRIME-LENGTH DISCRETE COSINE TRANSFORM
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GUO, JI; LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:04:24Z |
ON THE DESIGN AUTOMATION OF THE MEMORY-BASED VLSI ARCHITECTURES FOR FIR FILTERS
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LEE, HR; JEN, CW; LIU, CM |
| 國立交通大學 |
2014-12-08T15:04:22Z |
BINARY PARTITION ALGORITHMS AND VLSI ARCHITECTURES FOR MEDIAN AND RANK ORDER FILTERING
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LEE, CL; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:57Z |
CMOS THRESHOLD GATE AND NETWORKS FOR ORDER STATISTIC FILTERING
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LEE, CL; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:48Z |
EFFICIENT TIME-DOMAIN SYNTHESIS OF PIPELINED RECURSIVE FILTERS
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LAN, CP; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:25Z |
A NOVEL CORDIC-BASED ARRAY ARCHITECTURE FOR THE MULTIDIMENSIONAL DISCRETE HARTLEY TRANSFORM
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GUO, JI; LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:15Z |
A LOW-COST RASTER ENGINE FOR VIDEO GAME, MULTIMEDIA PC AND INTERACTIVE TV
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CHEN, CL; LIANG, BS; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:14Z |
SCALABLE ARRAY ARCHITECTURE DESIGN FOR FULL SEARCH BLOCK MATCHING
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CHANG, SF; HWANG, JH; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:08Z |
UNIFIED ARRAY ARCHITECTURE FOR DISCRETE COSINE TRANSFORM, SINE TRANSFORM AND THEIR INVERSES
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GUO, JI; CHEN, CS; JEN, CW |
| 國立交通大學 |
2014-12-08T15:02:42Z |
VASS - A VLSI array system synthesizer
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Yeh, JW; Cheng, WJ; Jen, CW |
显示项目 76-100 / 106 (共5页)
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