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"jen cw"的相關文件
顯示項目 21-45 / 106 (共5頁)
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| 國立交通大學 |
2014-12-08T15:43:18Z |
Hardware-efficient pipelined programmable FIR filter design
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Chang, TS; Jen, CW |
| 國立交通大學 |
2014-12-08T15:43:01Z |
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture
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Tuan, JC; Chang, TS; Jen, CW |
| 國立交通大學 |
2014-12-08T15:42:27Z |
Base model transmission for 3D graphics in a network environment
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Liang, BS; Jen, CW |
| 國立交通大學 |
2014-12-08T15:42:03Z |
Index rendering: Hardware-efficient architecture for 3-D graphics in multimedia system
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Liang, BS; Lee, YC; Yeh, WC; Jen, CW |
| 國立交通大學 |
2014-12-08T15:41:17Z |
Edge-preserving texture filtering for real-time rendering
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Lee, YC; Jen, CW |
| 國立交通大學 |
2014-12-08T15:41:14Z |
High-speed and low-power split-radix FFT
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Yeh, WC; Jen, CW |
| 國立交通大學 |
2014-12-08T15:41:10Z |
Motion estimation using MSD-first processing
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Su, CL; Jen, CW |
| 國立交通大學 |
2014-12-08T15:40:17Z |
Generalized earliest-first fast addition algorithm
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Yeh, WC; Jen, CW |
| 國立交通大學 |
2014-12-08T15:40:10Z |
MSD-first on-line arithmetic progressive processing implementation for motion estimation
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Su, CL; Jen, CW |
| 國立交通大學 |
2014-12-08T15:39:41Z |
Optimal frame memory and data transfer scheme for MPEG-4 shape coding
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Lee, KB; Chin, HY; Chang, NYC; Hsu, HC; Jen, CW |
| 國立交通大學 |
2014-12-08T15:35:06Z |
A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding
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Lee, KB; Lin, JY; Jen, CW |
| 國立交通大學 |
2014-12-08T15:27:57Z |
A NOVEL MEMORY ARCHITECTURE FOR VIDEO SIGNAL PROCESSOR
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HUNG, JS; LIN, CH; JEN, CW |
| 國立交通大學 |
2014-12-08T15:27:49Z |
A hardware-efficient architecture for 3-D graphics processor
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Liang, BS; Nieh, YC; Niou, YP; Jen, CW; Chuang, G |
| 國立交通大學 |
2014-12-08T15:27:49Z |
HARDWARE SHARING IN TREE-STRUCTURE QMF BANKS
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LEE, HR; JEN, CW |
| 國立交通大學 |
2014-12-08T15:27:49Z |
A RASTER ENGINE FOR COMPUTER GRAPHICS AND IMAGE COMPOSITION
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CHEN, CL; LIN, CH; LEE, HR; JEN, CW |
| 國立交通大學 |
2014-12-08T15:27:38Z |
The IC design of a high speed RSA processor
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Yang, CC; Jen, CW; Chang, TS |
| 國立交通大學 |
2014-12-08T15:27:37Z |
The IDCT processor on the Adder-Based distributed arithmetic
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Chen, CS; Chang, TS; Jen, CW |
| 國立交通大學 |
2014-12-08T15:27:33Z |
A programmable concurrent video signal processor
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Chen, CC; Jen, CW |
| 國立交通大學 |
2014-12-08T15:27:27Z |
An area and time efficient adder for multiple additions with different word-length
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Liang, BS; Nieh, YC; Jen, CW |
| 國立交通大學 |
2014-12-08T15:27:23Z |
A novel recursive digital filter based on signed digit distributed arithmetic
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Su, CL; Hwang, YT; Jen, CW |
| 國立交通大學 |
2014-12-08T15:27:17Z |
Hardware efficient transform designs with cyclic formulation and subexpression sharing
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Chang, TS; Jen, CW |
| 國立交通大學 |
2014-12-08T15:27:14Z |
Low power FIR filter realization with differential coefficients and input
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Chang, TS; Jen, CW |
| 國立交通大學 |
2014-12-08T15:27:14Z |
An architecture of full-search block matching for minimum memory bandwidth requirement
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Tuan, JC; Jen, CW |
| 國立交通大學 |
2014-12-08T15:27:06Z |
Data stream generation for concurrent computation in VLSI signal processors
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Lin, TJ; Jen, CW |
| 國立交通大學 |
2014-12-08T15:27:04Z |
A new hardware design and FPGA implementation for Internet routing towards IP over WDM and terabit routers
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Hsiao, IYL; Jen, CW |
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