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教育部委託研究計畫      計畫執行:國立臺灣大學圖書館
 
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機構 日期 題名 作者
國立交通大學 2019-04-02T05:59:54Z On-chip memory module designs for video-signal processing Chang, TS; Jen, CW
國立交通大學 2019-04-02T05:59:46Z Dynamic analysis of a two-gyro Anschutz compass Ge, ZM; Jen, CW; Ku, FN
國立交通大學 2019-04-02T05:58:25Z Low power design for MPEG-2 video decoder Lin, CH; Chen, CM; Jen, CW
國立交通大學 2019-04-02T05:58:23Z A new hardware-efficient architecture for programmable FIR filters Lee, HR; Jen, CW; Liu, CM
國立交通大學 2014-12-08T15:49:21Z Low power parallel Huffman decoding Lin, CH; Jen, CW
國立交通大學 2014-12-08T15:48:54Z New RSA cryptosystem hardware design based on Montgomery's algorithm Yang, CC; Chang, TS; Jen, CW
國立交通大學 2014-12-08T15:46:21Z New distributed arithmetic algorithm and its application to IDCT Chang, TS; Chen, C; Jen, CW
國立交通大學 2014-12-08T15:46:06Z Hardware-efficient implementations for discrete function transforms using LUT-based FPGAs Chang, TS; Jen, CW
國立交通大學 2014-12-08T15:45:43Z Low-power FIR filter realization with differential coefficients and inputs Chang, TS; Chu, YH; Jen, CW
國立交通大學 2014-12-08T15:45:30Z A simple processor core design for DCT/IDCT Chang, TS; Kung, CS; Jen, CW
國立交通大學 2014-12-08T15:45:04Z High-speed booth encoded parallel multiplier design Yeh, WC; Jen, CW
國立交通大學 2014-12-08T15:44:56Z Computation-effective 3-D graphics rendering architecture for embedded multimedia system Liang, BS; Jen, CW
國立交通大學 2014-12-08T15:44:50Z Hardware-efficient DFT designs with cyclic convolution and subexpression sharing Chang, TS; Guo, JI; Jen, CW
國立交通大學 2014-12-08T15:44:22Z Improved quadratic normal vector interpolation for realistic shading Lee, YC; Jen, CW
國立交通大學 2014-12-08T15:43:20Z Speed up of rendering pipeline by deferred lighting and triple queue structure Liang, BS; Jen, CW
國立交通大學 2014-12-08T15:43:18Z Hardware-efficient pipelined programmable FIR filter design Chang, TS; Jen, CW
國立交通大學 2014-12-08T15:43:01Z On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture Tuan, JC; Chang, TS; Jen, CW
國立交通大學 2014-12-08T15:42:27Z Base model transmission for 3D graphics in a network environment Liang, BS; Jen, CW
國立交通大學 2014-12-08T15:42:03Z Index rendering: Hardware-efficient architecture for 3-D graphics in multimedia system Liang, BS; Lee, YC; Yeh, WC; Jen, CW
國立交通大學 2014-12-08T15:41:17Z Edge-preserving texture filtering for real-time rendering Lee, YC; Jen, CW
國立交通大學 2014-12-08T15:41:14Z High-speed and low-power split-radix FFT Yeh, WC; Jen, CW
國立交通大學 2014-12-08T15:41:10Z Motion estimation using MSD-first processing Su, CL; Jen, CW
國立交通大學 2014-12-08T15:40:17Z Generalized earliest-first fast addition algorithm Yeh, WC; Jen, CW
國立交通大學 2014-12-08T15:40:10Z MSD-first on-line arithmetic progressive processing implementation for motion estimation Su, CL; Jen, CW
國立交通大學 2014-12-08T15:39:41Z Optimal frame memory and data transfer scheme for MPEG-4 shape coding Lee, KB; Chin, HY; Chang, NYC; Hsu, HC; Jen, CW
國立交通大學 2014-12-08T15:35:06Z A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding Lee, KB; Lin, JY; Jen, CW
國立交通大學 2014-12-08T15:27:57Z A NOVEL MEMORY ARCHITECTURE FOR VIDEO SIGNAL PROCESSOR HUNG, JS; LIN, CH; JEN, CW
國立交通大學 2014-12-08T15:27:49Z A hardware-efficient architecture for 3-D graphics processor Liang, BS; Nieh, YC; Niou, YP; Jen, CW; Chuang, G
國立交通大學 2014-12-08T15:27:49Z HARDWARE SHARING IN TREE-STRUCTURE QMF BANKS LEE, HR; JEN, CW
國立交通大學 2014-12-08T15:27:49Z A RASTER ENGINE FOR COMPUTER GRAPHICS AND IMAGE COMPOSITION CHEN, CL; LIN, CH; LEE, HR; JEN, CW
國立交通大學 2014-12-08T15:27:38Z The IC design of a high speed RSA processor Yang, CC; Jen, CW; Chang, TS
國立交通大學 2014-12-08T15:27:37Z The IDCT processor on the Adder-Based distributed arithmetic Chen, CS; Chang, TS; Jen, CW
國立交通大學 2014-12-08T15:27:33Z A programmable concurrent video signal processor Chen, CC; Jen, CW
國立交通大學 2014-12-08T15:27:27Z An area and time efficient adder for multiple additions with different word-length Liang, BS; Nieh, YC; Jen, CW
國立交通大學 2014-12-08T15:27:23Z A novel recursive digital filter based on signed digit distributed arithmetic Su, CL; Hwang, YT; Jen, CW
國立交通大學 2014-12-08T15:27:17Z Hardware efficient transform designs with cyclic formulation and subexpression sharing Chang, TS; Jen, CW
國立交通大學 2014-12-08T15:27:14Z Low power FIR filter realization with differential coefficients and input Chang, TS; Jen, CW
國立交通大學 2014-12-08T15:27:14Z An architecture of full-search block matching for minimum memory bandwidth requirement Tuan, JC; Jen, CW
國立交通大學 2014-12-08T15:27:06Z Data stream generation for concurrent computation in VLSI signal processors Lin, TJ; Jen, CW
國立交通大學 2014-12-08T15:27:04Z A new hardware design and FPGA implementation for Internet routing towards IP over WDM and terabit routers Hsiao, IYL; Jen, CW
國立交通大學 2014-12-08T15:27:04Z Motion estimation using on-line arithmetic Su, CL; Jen, CW
國立交通大學 2014-12-08T15:27:03Z A high performance carry-save to signed-digit recoder for fused addition-multiplication Yeh, WC; Jen, CW
國立交通大學 2014-12-08T15:27:03Z On the study of logarithmic time parallel adders Yeh, WC; Jen, CW
國立交通大學 2014-12-08T15:26:37Z Cascade-configurable and scalable DSP environment Lin, TJ; Jen, CW
國立交通大學 2014-12-08T15:26:36Z Design and implementation of a scalable fast Fourier transform core Sung, CH; Lee, KB; Jen, CW
國立交通大學 2014-12-08T15:26:30Z High-speed memory-saving architecture for the embedded block coding in JPEG2000 Hsiao, YT; Lin, HD; Lee, KB; Jen, CW
國立交通大學 2014-12-08T15:26:22Z An efficient VLIW DSP architecture for baseband processing Lin, TJ; Chang, CC; Lee, CC; Jen, CW
國立交通大學 2014-12-08T15:26:19Z Performance evaluation of ring-structure register file in multimedia applications Lin, TJ; Chang, CC; Yang, TH; Chang, YM; Lin, CH; Lee, CC; Lin, HY; Jen, CW
國立交通大學 2014-12-08T15:26:19Z Coefficient optimization for area-effective multiplier-less FIR filters Lin, TJ; Yang, TH; Jen, CW
國立交通大學 2014-12-08T15:26:16Z Area-effective FIR filter design for multiplier-less implementation Lin, TJ; Yang, TH; Jen, CW

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