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"jen cw"的相關文件
顯示項目 66-90 / 106 (共5頁)
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| 國立交通大學 |
2014-12-08T15:25:40Z |
A bandwidth and memory efficient MPEG-4 shape encoder
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Lee, KB; Chang, NYC; Chin, HY; Hsu, HC; Jen, CW |
| 國立交通大學 |
2014-12-08T15:25:38Z |
Lightweight arithmetic units for VLSI digital signal processors
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Ou, SH; Lin, TJ; Lin, HY; Chao, CM; Liu, CW; Jen, CW |
| 國立交通大學 |
2014-12-08T15:25:38Z |
A novel register organization for VLIW digital signal processors
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Lin, TJ; Lee, CC; Liu, CW; Jen, CW |
| 國立交通大學 |
2014-12-08T15:25:37Z |
Architecture for area-efficient 2-D transform in H.264/AVC
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Kuo, YT; Lin, TY; Liu, CW; Jen, CW |
| 國立交通大學 |
2014-12-08T15:25:24Z |
Hierarchical instruction encoding for VLIW digital signal processors
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Liu, CH; Lin, TJ; Chao, CM; Hsiao, PC; Lin, LC; Chen, SK; Huang, CW; Liu, CW; Jen, CW |
| 國立交通大學 |
2014-12-08T15:25:23Z |
Pipelining technique for energy-aware datapaths
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Huang, WS; Lin, TJ; Ou, SH; Liu, CW; Jen, CW |
| 國立交通大學 |
2014-12-08T15:19:40Z |
A memory-efficient realization of cyclic convolution and its application to discrete cosine transform
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Chen, HC; Guo, JI; Chang, TS; Jen, CW |
| 國立交通大學 |
2014-12-08T15:19:15Z |
An efficient quality-aware memory controller for multimedia platform SoC
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Lee, KB; Lin, TC; Jen, CW |
| 國立交通大學 |
2014-12-08T15:19:15Z |
The long length DHT design with a new hardware efficient distributed arithmetic approach and cyclic preserving partitioning
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Chen, HC; Chang, TS; Guo, JI; Jen, CW |
| 國立交通大學 |
2014-12-08T15:18:00Z |
Distributed arithmetic realisation of cyclic convolution and its DFT application
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Chen, HC; Guo, JI; Jen, CW; Chang, TS |
| 國立交通大學 |
2014-12-08T15:17:31Z |
A compact DSP core with static floating-point arithmetic
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Lin, TJ; Lin, HY; Chao, CM; Liu, CW; Jen, CW |
| 國立交通大學 |
2014-12-08T15:06:26Z |
DEPLETION WIDTHS OF THE METAL-INSULATOR SEMICONDUCTOR (MIS) STRUCTURE
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JEN, CW; LEE, CL; LEI, TF |
| 國立交通大學 |
2014-12-08T15:06:09Z |
MOTA - A MOSFET TIMING SIMULATOR
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JOU, SJ; JEN, CW; SHEN, WZ; LEE, CL |
| 國立交通大學 |
2014-12-08T15:06:03Z |
ELLIPSOMETRY MEASUREMENTS ON SIO2-FILMS FOR THICKNESSES UNDER 200-A
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HO, JH; LEE, CL; JEN, CW; LEI, TF |
| 國立交通大學 |
2014-12-08T15:06:02Z |
SIMULATABLE TIMING MODEL FOR MOS LOGIC-CIRCUIT
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JOU, SJ; SHEN, WZ; JEN, CW; LEE, CL |
| 國立交通大學 |
2014-12-08T15:05:56Z |
DESIGN OF A SYSTOLIC ARRAY SYSTEM FOR LINEAR STATE-EQUATIONS
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JOU, SJ; JEN, CW |
| 國立交通大學 |
2014-12-08T15:05:45Z |
DESIGN OF ALGORITHM-BASED FAULT-TOLERANT VLSI ARRAY PROCESSOR
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LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:05:43Z |
MULTI-DIMENSIONAL PARALLEL COMPUTING STRUCTURES FOR REGULAR ITERATIVE ALGORITHMS
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JEN, CW; KWAI, DM |
| 國立交通大學 |
2014-12-08T15:05:35Z |
REDUNDANCY DESIGN FOR A FAULT TOLERANT SYSTOLIC ARRAY
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WANG, JJ; JEN, CW |
| 國立交通大學 |
2014-12-08T15:05:33Z |
DESIGN OF ONE-DIMENSIONAL SYSTOLIC-ARRAY SYSTEMS FOR LINEAR STATE-EQUATIONS
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JEN, CW; JOU, SJ |
| 國立交通大學 |
2014-12-08T15:05:01Z |
BIT-SLICED MEDIAN FILTER DESIGN BASED ON MAJORITY GATE
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LEE, CL; JEN, CW |
| 國立交通大學 |
2014-12-08T15:05:00Z |
DATA FLOW REPRESENTATION OF ITERATIVE ALGORITHMS FOR SYSTOLIC ARRAYS
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JEN, CW; KWAI, DM |
| 國立交通大學 |
2014-12-08T15:04:50Z |
ON THE DESIGN OF VLSI ARRAYS FOR DISCRETE FOURIER-TRANSFORM
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LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:04:46Z |
THE EFFICIENT MEMORY-BASED VLSI ARRAY DESIGNS FOR DFT AND DCT
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GUO, JI; LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:04:44Z |
A PARALLEL ADAPTIVE ALGORITHM FOR MOVING TARGET DETECTION AND ITS VLSI ARRAY REALIZATION
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LIU, CM; JEN, CW |
顯示項目 66-90 / 106 (共5頁)
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