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"jen cw"的相關文件
顯示項目 81-105 / 106 (共5頁)
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| 國立交通大學 |
2014-12-08T15:05:56Z |
DESIGN OF A SYSTOLIC ARRAY SYSTEM FOR LINEAR STATE-EQUATIONS
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JOU, SJ; JEN, CW |
| 國立交通大學 |
2014-12-08T15:05:45Z |
DESIGN OF ALGORITHM-BASED FAULT-TOLERANT VLSI ARRAY PROCESSOR
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LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:05:43Z |
MULTI-DIMENSIONAL PARALLEL COMPUTING STRUCTURES FOR REGULAR ITERATIVE ALGORITHMS
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JEN, CW; KWAI, DM |
| 國立交通大學 |
2014-12-08T15:05:35Z |
REDUNDANCY DESIGN FOR A FAULT TOLERANT SYSTOLIC ARRAY
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WANG, JJ; JEN, CW |
| 國立交通大學 |
2014-12-08T15:05:33Z |
DESIGN OF ONE-DIMENSIONAL SYSTOLIC-ARRAY SYSTEMS FOR LINEAR STATE-EQUATIONS
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JEN, CW; JOU, SJ |
| 國立交通大學 |
2014-12-08T15:05:01Z |
BIT-SLICED MEDIAN FILTER DESIGN BASED ON MAJORITY GATE
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LEE, CL; JEN, CW |
| 國立交通大學 |
2014-12-08T15:05:00Z |
DATA FLOW REPRESENTATION OF ITERATIVE ALGORITHMS FOR SYSTOLIC ARRAYS
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JEN, CW; KWAI, DM |
| 國立交通大學 |
2014-12-08T15:04:50Z |
ON THE DESIGN OF VLSI ARRAYS FOR DISCRETE FOURIER-TRANSFORM
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LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:04:46Z |
THE EFFICIENT MEMORY-BASED VLSI ARRAY DESIGNS FOR DFT AND DCT
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GUO, JI; LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:04:44Z |
A PARALLEL ADAPTIVE ALGORITHM FOR MOVING TARGET DETECTION AND ITS VLSI ARRAY REALIZATION
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LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:04:40Z |
A NEW ARRAY ARCHITECTURE FOR PRIME-LENGTH DISCRETE COSINE TRANSFORM
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GUO, JI; LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:04:24Z |
ON THE DESIGN AUTOMATION OF THE MEMORY-BASED VLSI ARCHITECTURES FOR FIR FILTERS
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LEE, HR; JEN, CW; LIU, CM |
| 國立交通大學 |
2014-12-08T15:04:22Z |
BINARY PARTITION ALGORITHMS AND VLSI ARCHITECTURES FOR MEDIAN AND RANK ORDER FILTERING
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LEE, CL; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:57Z |
CMOS THRESHOLD GATE AND NETWORKS FOR ORDER STATISTIC FILTERING
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LEE, CL; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:48Z |
EFFICIENT TIME-DOMAIN SYNTHESIS OF PIPELINED RECURSIVE FILTERS
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LAN, CP; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:25Z |
A NOVEL CORDIC-BASED ARRAY ARCHITECTURE FOR THE MULTIDIMENSIONAL DISCRETE HARTLEY TRANSFORM
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GUO, JI; LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:15Z |
A LOW-COST RASTER ENGINE FOR VIDEO GAME, MULTIMEDIA PC AND INTERACTIVE TV
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CHEN, CL; LIANG, BS; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:14Z |
SCALABLE ARRAY ARCHITECTURE DESIGN FOR FULL SEARCH BLOCK MATCHING
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CHANG, SF; HWANG, JH; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:08Z |
UNIFIED ARRAY ARCHITECTURE FOR DISCRETE COSINE TRANSFORM, SINE TRANSFORM AND THEIR INVERSES
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GUO, JI; CHEN, CS; JEN, CW |
| 國立交通大學 |
2014-12-08T15:02:42Z |
VASS - A VLSI array system synthesizer
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Yeh, JW; Cheng, WJ; Jen, CW |
| 國立交通大學 |
2014-12-08T15:02:26Z |
Low power design for MPEG-2 video decoder
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Lin, CH; Chen, CM; Jen, CW |
| 國立交通大學 |
2014-12-08T15:02:24Z |
A new hardware-efficient architecture for programmable FIR filters
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Lee, HR; Jen, CW; Liu, CM |
| 國立交通大學 |
2014-12-08T15:02:09Z |
Dynamic analysis of a two-gyro Anschutz compass
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Ge, ZM; Jen, CW; Ku, FN |
| 國立交通大學 |
2014-12-08T15:01:44Z |
On-chip memory module designs for video-signal processing
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Chang, TS; Jen, CW |
| 國立交通大學 |
2014-12-08T15:01:35Z |
A multiplierless reconfigurable resizer for multi-window image display
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Huang, CM; Chang, TS; Jen, CW |
顯示項目 81-105 / 106 (共5頁)
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