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教育部委託研究計畫 計畫執行:國立臺灣大學圖書館
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"jen cw"的相關文件
顯示項目 91-100 / 106 (共11頁)
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每頁顯示[10|25|50]項目
| 國立交通大學 |
2014-12-08T15:04:40Z |
A NEW ARRAY ARCHITECTURE FOR PRIME-LENGTH DISCRETE COSINE TRANSFORM
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GUO, JI; LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:04:24Z |
ON THE DESIGN AUTOMATION OF THE MEMORY-BASED VLSI ARCHITECTURES FOR FIR FILTERS
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LEE, HR; JEN, CW; LIU, CM |
| 國立交通大學 |
2014-12-08T15:04:22Z |
BINARY PARTITION ALGORITHMS AND VLSI ARCHITECTURES FOR MEDIAN AND RANK ORDER FILTERING
|
LEE, CL; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:57Z |
CMOS THRESHOLD GATE AND NETWORKS FOR ORDER STATISTIC FILTERING
|
LEE, CL; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:48Z |
EFFICIENT TIME-DOMAIN SYNTHESIS OF PIPELINED RECURSIVE FILTERS
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LAN, CP; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:25Z |
A NOVEL CORDIC-BASED ARRAY ARCHITECTURE FOR THE MULTIDIMENSIONAL DISCRETE HARTLEY TRANSFORM
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GUO, JI; LIU, CM; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:15Z |
A LOW-COST RASTER ENGINE FOR VIDEO GAME, MULTIMEDIA PC AND INTERACTIVE TV
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CHEN, CL; LIANG, BS; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:14Z |
SCALABLE ARRAY ARCHITECTURE DESIGN FOR FULL SEARCH BLOCK MATCHING
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CHANG, SF; HWANG, JH; JEN, CW |
| 國立交通大學 |
2014-12-08T15:03:08Z |
UNIFIED ARRAY ARCHITECTURE FOR DISCRETE COSINE TRANSFORM, SINE TRANSFORM AND THEIR INVERSES
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GUO, JI; CHEN, CS; JEN, CW |
| 國立交通大學 |
2014-12-08T15:02:42Z |
VASS - A VLSI array system synthesizer
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Yeh, JW; Cheng, WJ; Jen, CW |
顯示項目 91-100 / 106 (共11頁)
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每頁顯示[10|25|50]項目
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