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Institution Date Title Author
臺大學術典藏 2020-06-11T06:29:48Z Rate-Optimal DSP Synthesis by Pipeline and Minimum Undolding. Jeng, Lih-Gwo;Chen, Liang-Gee; Jeng, Lih-Gwo; Chen, Liang-Gee; LIANG-GEE CHEN
臺大學術典藏 2018-09-10T04:47:25Z Application-specific chip design using behavioral silicon compiler Chen, Liang-Gee; Jeng, Lih-Gwo; Lin, Dong-Jye; LIANG-GEE CHEN; Chen, Liang-Gee;Jeng, Lih-Gwo;Lin, Dong-Jye
臺大學術典藏 2018-09-10T04:07:55Z Language system for DSP silicon compiler Chen, Liang-Gee; Jeng, Lih-Gwo; Tsao, Ki-Tsan; LIANG-GEE CHEN
臺大學術典藏 2018-09-10T03:43:47Z Optimal module set and clock cycle selection for DSP synthesis Chen, Liang-Gee;Jeng, Lih-Gwo; Chen, Liang-Gee; Jeng, Lih-Gwo; LIANG-GEE CHEN
臺大學術典藏 2018-07-06T13:44:40Z A globally static rate optimal scheduling for recursive DSP algorithms Jeng, Lih-Gwo; Chen, Liang-Gee; Jeng, Lih-Gwo; Chen, Liang-Gee
國立臺灣大學 1991-06 Optimal module set and clock cycle selection for DSP synthesis Chen, Liang-Gee; Jeng, Lih-Gwo
臺大學術典藏 1991-06 Optimal module set and clock cycle selection for DSP synthesis Chen, Liang-Gee; Jeng, Lih-Gwo; Chen, Liang-Gee; Jeng, Lih-Gwo
國立臺灣大學 1991-04 A globally static rate optimal scheduling for recursive DSP algorithms Jeng, Lih-Gwo; Chen, Liang-Gee
臺大學術典藏 1991 A globally static rate optimal scheduling for recursive DSP algorithms Jeng, Lih-Gwo; Chen, Liang-Gee; LIANG-GEE CHEN

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