臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

About TAIR
	About TAIR

Browse By
	Institution
	Author
	Title
	Date
	Statistics Chart
	Institution Facts
	Trend

News
	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

Copyright
	Publisher & Journal Policy
	TAIR Copyright Conference Minutes

Related Links
	機構典藏計畫網站
	ROAR
	OpenDOAR
	SHERPA
	OAIster
	JAIRO
	Ira
	DSPACE
	RWWR
	臺大學術典藏NTU Scholars

"jer min jou"

Return to Browse by Author
Sorting by Title	Sort by Date

Showing items 1-24 of 24 (1 Page(s) Totally)
1
View [10|25|50] records per page

Institution	Date	Title	Author
國立中山大學	2002-12	Design of A Dynamic Pipelined Architecture for Fuzzy Color Correction	Jer-Min Jou;Shiann-Rong Kuang;Yeu-Horng Shiau;Ren-Der Chen
國立中山大學	2002-07	A Low Cost Gray Prediction Search Chip for Motion Estimation	Jer-Min Jou;Yeu-Horng Shiau;Pei-Yin Chen;Shiann-Rong Kuang
國立中山大學	2001-09	Dynamic Pipeline Design of an Adaptive Binary Arithmetic Coder	Shiann-Rong Kuang;Jer-Min Jou;Ren-Der Chen;Yeu-Horng Shiau
國立中山大學	1999-06	Design of Low-Error Fixed-Width Multipliers for DSP Applications	Jer-Min Jou;Shiann-Rong Kuang;Ren-Der Chen
國立中山大學	1999-06	A New Efficient Fuzzy Algorithm for Color Correction	Jer-Min Jou;Shiann-Rong Kuang;Ren-Der Chen
南台科技大學	1999-02	An Efficient Search Algorithm for Block-Matching Motion Estimation	Pei-Yin Chen; Jer Min Jou; Shung-Chih Chen
國立中山大學	1998-07	The Design of an Adaptive On-Line Binary Arithmetic Coding Chip	Shiann-Rong Kuang;Jer-Min Jou;Yuh-Lin Chen
南台科技大學	1998-05	Fast Delay-Dependent Power Estimation of Large Combinational Circuits	Jer Min Jou; Shung-Chih Chen; Chih-Liang Wang; 陳順智
南台科技大學	1997-11	Serial Diagnostic Fault Simulation for Synchronous Sequential Circuits	Shung-Chih Chen; Jer-Min Jou;陳順智
南台科技大學	1997-03	Diagnostic Fault Simulation for Synchronous Sequential Circuits	Shung-Chih Chen; Jer Min Jou;陳順智
國立中山大學	1997	Design of a low-error fixed-width multiplier for DSP applications	Jer-Min Jou;Shiann-Rong Kuang
南台科技大學	1996-08	Hierarchical Power Estimation of Digital Circuits	Jer Min Jou; R, -H, Hung; Shung-Chih Chen
南台科技大學	1995-05	Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning	Jer Min Jou; Shung-Chih Chen; 陳順智
國立中山大學	1995-05	A Library-Adaptively Integrated High Level Synthesis System	Jer-Min Jou;Shiann-Rong Kuang
國立中山大學	1995-05	A Library-Adaptively Integrated High Level Synthesis System	Jer-Min Jou;Shiann-Rong Kuang
南台科技大學	1994-06	A New Fault Simulator for Large Synchronous Sequential Circuits	Jer Min Jou; Shung-Chih Chen; 陳順智
南台科技大學	1994-06	An Improved Diagnostic Fault Simulation for Sequential Circuits	Jer Min Jou; Shung-Chih Chen; 陳順智
南台科技大學	1994-06	Efficient diagnostic fault simulation for sequential circuits	Jer Min Jou; Shung-Chih Chen; 孫建明;陳順智
南台科技大學	1994-05	A Super Fast and Memory Efficient Diagnostic Simulation Algorithm for Combinational Circuits	Jer Min Jou; Shung-Chih Chen; Ren-Der Chen; 陳順智
南台科技大學	1994-04	A Fast and Memory-Efficient Diagnostic Fault Simulation for Sequential Circuits	Jer Min Jou; Shung-Chih Chen; 孫建明;陳順智
南台科技大學	1993-05	PARCRIPT: a very fast combinational fault simulator	Jer Min Jou; Shung-Chih Chen; 孫建明;陳順智
南台科技大學	1992-03	An Efficient VHDL Simulator with Two-Simulation-Run Ability	Jer Min Jou; Shung-Chih Chen
南台科技大學	1992-01	MASS: An Integrated Approach to High Level Synthesis	Jer Min Jou; S. R. Kuang; Shung-Chih Chen
南台科技大學	1991-12	An Efficient Mixed-level VHDL Simulator with Robust Debugging Capability	Jer Min Jou; Shung-Chih Chen

Showing items 1-24 of 24 (1 Page(s) Totally)
1
View [10|25|50] records per page

	English \| 正體中文 \| 简体中文 \| Total items :0
	Visitors : 51746655 Online Users : 1074 Project Commissioned by the Ministry of Education Project Executed by National Taiwan University Library