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Showing items 11-15 of 15 (1 Page(s) Totally)
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| 國立交通大學 |
2014-12-08T15:26:45Z |
Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology
|
Ker, MD; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:26:38Z |
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits
|
Peng, JJ; Ker, MD; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:26:36Z |
Design of negative charge pump circuit with polysilicon diodes in a 0.25-mu m CMOS process
|
Ker, MD; Chang, CY; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:26:28Z |
Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution
|
Ker, MD; Peng, JJ; Jiang, HC |
| 國立交通大學 |
2014-12-08T15:26:13Z |
Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOCIC's
|
Ker, MD; Peng, JJ; Jiang, HC |
Showing items 11-15 of 15 (1 Page(s) Totally)
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