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Showing items 1-25 of 52 (3 Page(s) Totally)
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| 臺大學術典藏 |
2020-06-11T06:12:49Z |
3DICE: 3D IC cost evaluation based on fast tier number estimation
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Chan, C.-C.;Yu, Y.-T.;Jiang, I.H.-R.; Chan, C.-C.; Yu, Y.-T.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:10Z |
A Dynamic Programming Approach to Optimal Lane Merging of Connected and Autonomous Vehicles
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Lin S.-C;Hsu H;Lin Y.-T;Lin C.-W;Jiang I.H.-R;Liu C.; Lin S.-C; Hsu H; Lin Y.-T; Lin C.-W; Jiang I.H.-R; Liu C.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:49Z |
Analog placement and global routing considering wiring symmetry
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Yang, Y.-M.;Jiang, I.H.-R.; Yang, Y.-M.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:57Z |
Analytical Clustering score with application to post-placement multi-bit flip-flop merging
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Xu, C.;Li, P.;Luo, G.;Shi, Y.;Jiang, I.H.-R.; Xu, C.; Li, P.; Luo, G.; Shi, Y.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:57Z |
Criticality-dependency-aware timing characterization and analysis
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Yang, Y.-M.;Tam, K.H.;Jiang, I.H.-R.; Yang, Y.-M.; Tam, K.H.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2018-09-10T03:29:37Z |
Crosstalkdriven interconnect optimization by simultaneous gate and wire sizing
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Jiang, I.H.R.; Chang, Y.W.; Jou, J.Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2021-09-02T00:05:11Z |
DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design
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Chen J;Jiang I.H.-R;Jung J;Kahng A.B;Kravets V.N;Li Y.-L;Lin S.-T;Woo M.; Chen J; Jiang I.H.-R; Jung J; Kahng A.B; Kravets V.N; Li Y.-L; Lin S.-T; Woo M.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:46Z |
DRC-based hotspot detection considering edge tolerance and incomplete specification
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Yu, Y.-T.;Jiang, I.H.-R.;Zhang, Y.;Chiang, C.; Yu, Y.-T.; Jiang, I.H.-R.; Zhang, Y.; Chiang, C.; HUI-RU JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:11Z |
Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance
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Huang X.-X;Chen H.-C;Wang S.-W;Jiang I.H.-R;Chou Y.-C;Tsai C.-H.; Huang X.-X; Chen H.-C; Wang S.-W; Jiang I.H.-R; Chou Y.-C; Tsai C.-H.; HUI-RU JIANG |
| 臺大學術典藏 |
2018-09-10T09:48:08Z |
ECO optimization using metal-configurable gate-array spare cells
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Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2020-06-11T06:12:52Z |
ECO optimization using metal-configurable gate-array spare cells
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Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:57Z |
Efficient coverage-driven stimulus generation using simultaneous SAT solving, with application to SystemVerilog
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Cheng, A.-C.;Yen, C.-C.;Val, C.G.;Bayless, S.;Hu, A.J.;Jiang, I.H.-R.;Jou, J.-Y.; Cheng, A.-C.; Yen, C.-C.; Val, C.G.; Bayless, S.; Hu, A.J.; Jiang, I.H.-R.; Jou, J.-Y.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:45Z |
FastPass: Fast timing path search for generalized timing exception handling
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Lee, P.-Y.;Jiang, I.H.-R.;Chen, T.-C.HUI-RU JIANG;Chen, T.-C.;Jiang, I.H.-R.;Lee, P.-Y.; Lee, P.-Y.; Jiang, I.H.-R.; Chen, T.-C.; HUI-RU JIANG |
| 國立交通大學 |
2015-12-02T02:59:13Z |
Feature detection for image analytics via FPGA acceleration
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Chang, H. -Y.; Jiang, I. H. -R.; Hofstee, H. P.; Jamsek, D.; Nam, G. -J. |
| 臺大學術典藏 |
2020-06-11T06:12:59Z |
Feature detection for image analytics via FPGA acceleration
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Chang, H.-Y.;Jiang, I.H.-R.;Hofstee, H.P.;Jamsek, D.;Nam, G.-J.; Chang, H.-Y.; Jiang, I.H.-R.; Hofstee, H.P.; Jamsek, D.; Nam, G.-J.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:56Z |
FF-bond: Multi-bit flip-flop bonding at placement
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Tsai, C.-C.;Shi, Y.;Luo, G.;Jiang, I.H.-R.; Tsai, C.-C.; Shi, Y.; Luo, G.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2018-09-10T14:57:59Z |
Functional ECO using metal-configurable gate-array spare cells
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Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2020-06-11T06:12:57Z |
Functional ECO using metal-configurable gate-array spare cells
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Chang, H.-Y.;Jiang, I.H.-R.;Chang, Y.-W.; Chang, H.-Y.; Jiang, I.H.-R.; Chang, Y.-W.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:47Z |
GasStation: Power and area efficient buffering for multiple power domain design
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Lu, C.-P.;Jiang, I.H.-R.;Hsu, C.-H.; Lu, C.-P.; Jiang, I.H.-R.; Hsu, C.-H.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:50Z |
Generic integer linear programming formulation for 3D IC partitioning
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Jiang, I.H.-R.; Jiang, I.H.-R.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:59Z |
Graph-based modeling, scheduling, and verification for intersection management of intelligent vehicles
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Lin, Y.-T.;Hsu, H.;Lin, S.-C.;Lin, C.-W.;Jiang, I.H.-R.;Liu, C.; Lin, Y.-T.; Hsu, H.; Lin, S.-C.; Lin, C.-W.; Jiang, I.H.-R.; Liu, C.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:54Z |
INTEGRA: Fast multi-bit flip-flop clustering for clock power saving based on interval graphs
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Jiang, I.H.-R.;Chang, C.-L.;Yang, Y.-M.;Tsai, E.Y.-W.;Chen, L.S.-F.; Jiang, I.H.-R.; Chang, C.-L.; Yang, Y.-M.; Tsai, E.Y.-W.; Chen, L.S.-F.; HUI-RU JIANG |
| 臺大學術典藏 |
2020-06-11T06:12:51Z |
INTEGRA: Fast multibit flip-flop clustering for clock power saving
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Jiang, I.H.-R.;Chang, C.-L.;Yang, Y.-M.; Jiang, I.H.-R.; Chang, C.-L.; Yang, Y.-M.; HUI-RU JIANG |
| 臺大學術典藏 |
2021-09-02T00:04:37Z |
Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration
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Jiang I.H.-R;Chang Y.-W;Huang J.-L;Chen C.-P.; Jiang I.H.-R; Chang Y.-W; Huang J.-L; Chen C.-P.; CHUNG-PING CHEN |
| 臺大學術典藏 |
2021-09-02T00:05:11Z |
Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration
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Jiang I.H.-R;Chang Y.-W;Huang J.-L;Chen C.-P.; Jiang I.H.-R; Chang Y.-W; Huang J.-L; Chen C.-P.; HUI-RU JIANG |
Showing items 1-25 of 52 (3 Page(s) Totally)
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