|
English
|
正體中文
|
简体中文
|
2809390
|
|
???header.visitor??? :
27005103
???header.onlineuser??? :
953
???header.sponsordeclaration???
|
|
|
???tair.name??? >
???browser.page.title.author???
|
"jiang ihr"???jsp.browse.items-by-author.description???
Showing items 1-5 of 5 (1 Page(s) Totally) 1 View [10|25|50] records per page
國立交通大學 |
2014-12-08T15:46:03Z |
Internet-based hierarchical floorplan design
|
Lin, JH; Jou, JY; Jiang, IHR |
國立交通大學 |
2014-12-08T15:44:51Z |
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
|
Jiang, IHR; Chang, YW; Jou, JY |
國立交通大學 |
2014-12-08T15:39:16Z |
Simultaneous floorplan and buffer-block optimization
|
Jiang, IHR; Chang, YW; Jou, JY; Chao, KY |
國立交通大學 |
2014-12-08T15:26:50Z |
On placement and routing of wafer scale memory
|
Sung, LA; Jiang, IHR; Chang, YW; Jou, JY; Wu, JC; Feng, TS |
國立交通大學 |
2014-12-08T15:17:44Z |
Reliable crosstalk-driven interconnect optimization
|
Jiang, IHR; Pan, SR; Chang, YW; Jou, JY |
Showing items 1-5 of 5 (1 Page(s) Totally) 1 View [10|25|50] records per page
|