| 國立交通大學 |
2014-12-08T15:21:18Z |
3DICE: 3D IC Cost Evaluation Based on Fast Tier Number Estimation
|
Chan, Cheng-Chi; Yu, Yen-Ting; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:28:24Z |
Accurate Process-Hotspot Detection Using Critical Design Rule Extraction
|
Yu, Yen-Ting; Chan, Ya-Chung; Sinha, Subarna; Jiang, Iris Hui-Ru; Chiang, Charles |
| 國立交通大學 |
2017-04-21T06:48:38Z |
Analog Placement and Global Routing Considering Wiring Symmetry
|
Yang, Yu-Ming; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2017-04-21T06:55:43Z |
Analytical Clustering Score with Application to Postplacement Register Clustering
|
Xu, Chang; Luo, Guojie; Li, Peixin; Shi, Yiyu; Jiang, Iris Hui-Ru |
| 臺大學術典藏 |
2018-09-10T07:36:58Z |
Clustering- and probability-based approach for time-multiplexed FPGA partitioning
|
Chang, Yao-Wen; YAO-WEN CHANG; Jiang, Iris Hui-Ru; Chao, Mango Chia-Tso; Wu, Guang-Ming |
| 國立交通大學 |
2014-12-08T15:47:58Z |
Configurable Rectilinear Steiner Tree Construction for SoC and Nano Technologies
|
Jiang, Iris Hui-Ru; Yu, Yen-Ting |
| 國立交通大學 |
2017-04-21T06:49:13Z |
Criticality-Dependency-Aware Timing Characterization and Analysis
|
Yang, Yu-Ming; Tam, King Ho; Jiang, Iris Hui-Ru |
| 國立臺灣大學 |
2000 |
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
|
Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang |
| 臺大學術典藏 |
2018-09-10T03:29:38Z |
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
|
Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG |
| 國立交通大學 |
2020-05-05T00:02:00Z |
DATC RDF-2019: Towards a Complete Academic Reference Design Flow
|
Lin, Shih-Ting; Woo, Mingyu; Li, Yih-Lang; Jiang, Iris Hui-Ru; Jung, Jinwook; Kahng, Andrew B.; Kravets, Victor N.; Chen, Jianli |
| 國立交通大學 |
2019-12-13T01:12:53Z |
DATC RDF: An Academic Flow from Logic Synthesis to Detailed Routing
|
Jung, Jinwook; Jiang, Iris Hui-Ru; Chen, Jianli; Lin, Shih-Ting; Li, Yih-Lang; Kravets, Victor N.; Nam, Gi-Joon |
| 國立交通大學 |
2018-08-21T05:56:59Z |
DATC RDF: Robust Design Flow Database
|
Jung, Jinwook; Lee, Pei-Yu; Wu, Yan-Shiun; Darav, Nima Karimpour; Jiang, Iris Hui-Ru; Kravets, Victor N.; Behjat, Laleh; Li, Yih-Lang; Nam, Gi-Joon |
| 國立交通大學 |
2017-04-21T06:50:11Z |
DRC-Based Hotspot Detection Considering Edge Tolerance and Incomplete Specification
|
Yu, Yen-Ting; Jiang, Iris Hui-Ru; Zhang, Yumin; Chiang, Charles |
| 國立交通大學 |
2014-12-08T15:21:55Z |
ECOS: Stable Matching Based Metal-Only ECO Synthesis
|
Jiang, Iris Hui-Ru; Chang, Hua-Yu |
| 國立交通大學 |
2015-07-21T11:21:09Z |
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog
|
Cheng, An-Che; Yen, Chia-Chih (Jack); Val, Celina G.; Bayless, Sam; Hu, Alan J.; Jiang, Iris Hui-Ru; Jou, Jing-Yang |
| 國立交通大學 |
2019-01-01 |
Efficient Search of Layout Hotspot Patterns for Matching SEM Images using Multilevel Pixelation
|
Chang, Wei-Chun; Jiang, Iris Hui-Ru; Zhu, Jun; Shiely, James P.; Tseng, Sean Shang-En |
| 國立交通大學 |
2018-08-21T05:56:49Z |
Fast Low Power Rule Checking for Multiple Power Domain Design
|
Lu, Chien-Pang; Jiang, Iris Hui-Ru |
| 國立交通大學 |
2018-08-21T05:57:09Z |
FastPass: Fast Timing Path Search for Generalized Timing Exception Handling
|
Lee, Pei-Yu; Jiang, Iris Hui-Ru; Chen, Tung-Chieh |
| 國立交通大學 |
2017-04-21T06:48:45Z |
Functional ECO Using Metal-Configurable Gate-Array Spare Cells
|
Chang, Hua-Yu; Jiang, Iris Hui-Ru; Chang, Yao-Wen |
| 國立交通大學 |
2016-03-28T00:05:45Z |
GasStation: Power and Area Efficient Buffering for Multiple Power Domain Design
|
Lu, Chien-Pang; Jiang, Iris Hui-Ru; Hsu, Chin-Hsiung |
| 國立交通大學 |
2014-12-08T15:23:14Z |
GENERIC INTEGER LINEAR PROGRAMMING FORMULATION FOR 3D IC PARTITIONING
|
Jiang, Iris Hui-Ru |
| 國立交通大學 |
2014-12-08T15:28:32Z |
Generic Integer Linear Programming Formulation for 3D IC Partitioning
|
Lee, Wan-Yu; Jiang, Iris Hui-Ru; Mei, Tsung-Wan |
| 國立交通大學 |
2019-08-02T02:14:47Z |
Graceful Register Clustering by Effective Mean Shift Algorithm for Power and Timing Balancing
|
Chang, Ya-Chu; Lin, Tung-Wei; Jiang, Iris Hui-Ru; Nam, Gi-Joon |
| 臺大學術典藏 |
2020-05-04T07:53:49Z |
Graph-Based Modeling, Scheduling, and Verification for Intersection Management of Intelligent Vehicles.
|
Lin, Chung-Wei; Jiang, Iris Hui-Ru; Liu, Changliu; CHUNG-WEI LIN; Lin, Shang-Chien; Hsu, Hsiang; Lin, Yi-Ting; Lin, Yi-Ting;Hsu, Hsiang;Lin, Shang-Chien;Lin, Chung-Wei;Jiang, Iris Hui-Ru;Liu, Changliu |
| 國立交通大學 |
2018-08-21T05:57:00Z |
iClaire: A Fast and General Layout Pattern Classification Algorithm
|
Chang, Wei-Chun; Jiang, Iris Hui-Ru; Yu, Yen-Ting; Liu, Wei-Fang |
