| 臺大學術典藏 |
2021-09-02T00:05:34Z |
Time multiplexing via circuit folding
|
Chien P.-C;Jiang J.-H.R.; Chien P.-C; Jiang J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:34Z |
Symbolic Uniform Sampling with XOR Circuits
|
Lin Y.-T;Jiang J.-H.R;Kravets V.N.; Lin Y.-T; Jiang J.-H.R; Kravets V.N.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:33Z |
SFO: A scalable approach to fanout-bounded logic synthesis for emerging technologies
|
Zhang H.-T;Jiang J.-H.R.; Zhang H.-T; Jiang J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:33Z |
Symbolic gas vulnerability detection and attack synthesis
|
Peng M.H;Yu F;Jiang J.H.R.; Peng M.H; Yu F; Jiang J.H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:33Z |
SAT-Based On-Track Bus Routing
|
Zhang H.-T;Fujita M;Cheng C.-K;Jiang J.-H.R.; Zhang H.-T; Fujita M; Cheng C.-K; Jiang J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:33Z |
Symbolic gas vulnerability detection and attack synthesis
|
Peng M.H;Yu F;Jiang J.H.R.; Peng M.H; Yu F; Jiang J.H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:32Z |
Circuit learning for logic regression on high dimensional boolean space
|
Chen P.-W;Huang Y.-C;Lee C.-L;Jiang J.-H.R.; Chen P.-W; Huang Y.-C; Lee C.-L; Jiang J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:32Z |
Constraint Solving for Synthesis and Verification of Threshold Logic Circuits
|
Lee N.-Z;Jiang J.-H.R.; Lee N.-Z; Jiang J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:32Z |
Mining Biochemical Circuits from Enzyme Databases via Boolean Reasoning
|
Lin Y.-C;Jiang J.-H.R.; Lin Y.-C; Jiang J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:44:54Z |
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization
|
Chang, C.-W.;Chou, H.-Z.;Chang, K.-H.;Jiang, J.-H.R.;Liu, C.-N.J.;Hsiao, C.-H.;Kuo, S.-Y.; Chang, C.-W.; Chou, H.-Z.; Chang, K.-H.; Jiang, J.-H.R.; Liu, C.-N.J.; Hsiao, C.-H.; Kuo, S.-Y.; SY-YEN KUO |
| 臺大學術典藏 |
2020-06-11T06:11:17Z |
Disjoint-support decomposition and extraction for interconnect-driven threshold logic synthesis
|
Chen, H.;Hung, S.-C.;Jiang, J.-H.R.; Chen, H.; Hung, S.-C.; Jiang, J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:17Z |
Comprehensive search for ECO rectification using symbolic sampling
|
Kravets, V.N.;Lee, N.-Z.;Jiang, J.-H.R.; Kravets, V.N.; Lee, N.-Z.; Jiang, J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:14Z |
Recombinase-based genetic circuit optimization
|
Lai, C.-N.;Jiang, J.-H.R.;Fages, F.; Lai, C.-N.; Jiang, J.-H.R.; Fages, F.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:12Z |
Bi-decomposition using SAT and interpolation
|
Lee, R.-R.;Jiang, J.-H.R.;Hung, W.-L.; Lee, R.-R.; Jiang, J.-H.R.; Hung, W.-L.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:11Z |
Extracting functions from boolean relations using SAT and interpolation
|
Jiang, J.-H.R.;Lin, H.-P.;Hung, W.-L.; Jiang, J.-H.R.; Lin, H.-P.; Hung, W.-L.; JIE-HONG JIANG |
| 臺大學術典藏 |
2019-04-22T05:22:34Z |
Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction
|
Jiang, J.-H.R.;Li, J.C.M.;Pai, Y.-C.;Wen, H.-T.;Wang, J.-J.;Pai, C.-C.;Wang, R.-Y.;Chang, Y.-W.; Wang, R.-Y.; Pai, C.-C.; Wang, J.-J.; Wen, H.-T.; Pai, Y.-C.; Chang, Y.-W.; Li, J.C.M.; Jiang, J.-H.R. |
| 臺大學術典藏 |
2018-09-10T15:33:10Z |
Simultaneous EUV flare variation minimization and CMP control by coupling-aware dummification
|
Chiang, H.-J.K.; Liu, C.-Y.; Jiang, J.-H.R.; Chang, Y.-W.; Chiang, H.-J.K.; Liu, C.-Y.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T09:22:25Z |
TRECO: Dynamic technology remapping for timing engineering change orders
|
Ho, K.-H.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T06:31:03Z |
A statistical approach to the timing-yield optimization of pipeline circuits
|
Hsu, C.-H.; Chou, S.-J.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG |
| 國立臺灣大學 |
2010 |
To SAT or Not to SAT: Scalable Exploration of Functional Dependency
|
Jiang, J.-H.R.; Lee, Chih-Chun; Mishchenko, A.; Huang, Chung-Yang |
