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Institution Date Title Author
臺大學術典藏 2020-06-11T06:11:16Z Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. Chuang, Chi-Chuan;Lai, Yi-Hsiang;Jiang, Jie-Hong R.; Chuang, Chi-Chuan; Lai, Yi-Hsiang; Jiang, Jie-Hong R.; JIE-HONG JIANG
臺大學術典藏 2020-06-11T06:11:15Z Automatic test pattern generation for delay defects using timed characteristic functions. Ho, Shin-Yann;Lin, Shuo-Ren;Yuan, Ko-Lung;Kuo, Chien-Yen;Liao, Kuan-Yu;Jiang, Jie-Hong R.;Li, Chien-Mo James; Ho, Shin-Yann; Lin, Shuo-Ren; Yuan, Ko-Lung; Kuo, Chien-Yen; Liao, Kuan-Yu; Jiang, Jie-Hong R.; Li, Chien-Mo James; JIE-HONG JIANG
臺大學術典藏 2020-06-11T06:11:15Z Encoding multi-valued functions for symmetry. Yuan, Ko-Lung;Kuo, Chien-Yen;Jiang, Jie-Hong R.;Li, Meng-Yen; Yuan, Ko-Lung; Kuo, Chien-Yen; Jiang, Jie-Hong R.; Li, Meng-Yen; JIE-HONG JIANG
臺大學術典藏 2020-06-11T06:11:13Z Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits. Chang, Yi-Fan Evan;Huang, Ruei-Yang;Jiang, Jie-Hong R.; Chang, Yi-Fan Evan; Huang, Ruei-Yang; Jiang, Jie-Hong R.; JIE-HONG JIANG
臺大學術典藏 2020-06-11T06:11:12Z A Cube Distribution Approach to QBF Solving and Certificate Minimization. Chen, Li-Cheng;Jiang, Jie-Hong R.; Chen, Li-Cheng; Jiang, Jie-Hong R.; JIE-HONG JIANG
國立政治大學 2018-07 A Symbolic Model Checking Approach to the Analysis of String and Length Constraints 郁方; Yu, Fang; Wang, Hung-En;Chen, Shih-Yu;Yu, Fang;Jiang, Jie-Hong R.
國立臺灣大學 2010 Hardware Equivalence and Property Verification Jiang, Jie-Hong R.; Villa, Tiziano
國立臺灣大學 2009 Logic Synthesis in a Nutshell Jiang, Jie-Hong R.; Devadas, Srinivas
國立臺灣大學 2005-11-04 Applied Logic & Computation for System Design- An introductory invitation Jiang, Jie-Hong R.; 江介宏
臺大學術典藏 2005-11-04 Applied Logic & Computation for System Design- An introductory invitation 江介宏; Jiang, Jie-Hong R.; Jiang, Jie-Hong R.

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