| 臺大學術典藏 |
2021-09-02T00:05:34Z |
Time multiplexing via circuit folding
|
Chien P.-C;Jiang J.-H.R.; Chien P.-C; Jiang J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:34Z |
Symbolic Uniform Sampling with XOR Circuits
|
Lin Y.-T;Jiang J.-H.R;Kravets V.N.; Lin Y.-T; Jiang J.-H.R; Kravets V.N.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:33Z |
SFO: A scalable approach to fanout-bounded logic synthesis for emerging technologies
|
Zhang H.-T;Jiang J.-H.R.; Zhang H.-T; Jiang J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:33Z |
Symbolic gas vulnerability detection and attack synthesis
|
Peng M.H;Yu F;Jiang J.H.R.; Peng M.H; Yu F; Jiang J.H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:33Z |
SAT-Based On-Track Bus Routing
|
Zhang H.-T;Fujita M;Cheng C.-K;Jiang J.-H.R.; Zhang H.-T; Fujita M; Cheng C.-K; Jiang J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:33Z |
Symbolic gas vulnerability detection and attack synthesis
|
Peng M.H;Yu F;Jiang J.H.R.; Peng M.H; Yu F; Jiang J.H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:32Z |
Circuit learning for logic regression on high dimensional boolean space
|
Chen P.-W;Huang Y.-C;Lee C.-L;Jiang J.-H.R.; Chen P.-W; Huang Y.-C; Lee C.-L; Jiang J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:32Z |
Constraint Solving for Synthesis and Verification of Threshold Logic Circuits
|
Lee N.-Z;Jiang J.-H.R.; Lee N.-Z; Jiang J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:32Z |
Mining Biochemical Circuits from Enzyme Databases via Boolean Reasoning
|
Lin Y.-C;Jiang J.-H.R.; Lin Y.-C; Jiang J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2021-09-02T00:05:32Z |
Homing Sequence Derivation with Quantified Boolean Satisfiability
|
Tu K;Wang H;Jiang J.R;Kushik N;Yevtushenko N.; Tu K; Wang H; Jiang J.R; Kushik N; Yevtushenko N.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:17Z |
Disjoint-support decomposition and extraction for interconnect-driven threshold logic synthesis
|
Chen, H.;Hung, S.-C.;Jiang, J.-H.R.; Chen, H.; Hung, S.-C.; Jiang, J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:17Z |
Comprehensive search for ECO rectification using symbolic sampling
|
Kravets, V.N.;Lee, N.-Z.;Jiang, J.-H.R.; Kravets, V.N.; Lee, N.-Z.; Jiang, J.-H.R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:17Z |
A PSPACE Subclass of Dependency Quantified Boolean Formulas and Its Effective Solving.
|
Scholl, Christoph;Jiang, Jie-Hong Roland;Wimmer, Ralf;Ge-Ernst, Aile; Scholl, Christoph; Jiang, Jie-Hong Roland; Wimmer, Ralf; Ge-Ernst, Aile; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:16Z |
Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits.
|
Chuang, Chi-Chuan;Lai, Yi-Hsiang;Jiang, Jie-Hong R.; Chuang, Chi-Chuan; Lai, Yi-Hsiang; Jiang, Jie-Hong R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:15Z |
Automatic test pattern generation for delay defects using timed characteristic functions.
|
Ho, Shin-Yann;Lin, Shuo-Ren;Yuan, Ko-Lung;Kuo, Chien-Yen;Liao, Kuan-Yu;Jiang, Jie-Hong R.;Li, Chien-Mo James; Ho, Shin-Yann; Lin, Shuo-Ren; Yuan, Ko-Lung; Kuo, Chien-Yen; Liao, Kuan-Yu; Jiang, Jie-Hong R.; Li, Chien-Mo James; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:15Z |
Encoding multi-valued functions for symmetry.
|
Yuan, Ko-Lung;Kuo, Chien-Yen;Jiang, Jie-Hong R.;Li, Meng-Yen; Yuan, Ko-Lung; Kuo, Chien-Yen; Jiang, Jie-Hong R.; Li, Meng-Yen; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:15Z |
Synthesis of Nondeterministic Behavior in Recombinase-Based Genetic Circuits.
|
Lin, Zi-Jun;Huang, Wei-Chih;Jiang, Jie-Hong Roland; Lin, Zi-Jun; Huang, Wei-Chih; Jiang, Jie-Hong Roland; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:14Z |
Recombinase-based genetic circuit optimization
|
Lai, C.-N.;Jiang, J.-H.R.;Fages, F.; Lai, C.-N.; Jiang, J.-H.R.; Fages, F.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:13Z |
Effective FPGA Resource Utilization for Quasi Delay Insensitive Implementation of Asynchronous Circuits.
|
Chang, Yi-Fan Evan;Huang, Ruei-Yang;Jiang, Jie-Hong R.; Chang, Yi-Fan Evan; Huang, Ruei-Yang; Jiang, Jie-Hong R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:12Z |
A Cube Distribution Approach to QBF Solving and Certificate Minimization.
|
Chen, Li-Cheng;Jiang, Jie-Hong R.; Chen, Li-Cheng; Jiang, Jie-Hong R.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:12Z |
Bi-decomposition using SAT and interpolation
|
Lee, R.-R.;Jiang, J.-H.R.;Hung, W.-L.; Lee, R.-R.; Jiang, J.-H.R.; Hung, W.-L.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:12Z |
Logic Synthesis in a Nutshell
|
Jiang, J.H.;Devadas, S.; Jiang, J.H.; Devadas, S.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:11Z |
Extracting functions from boolean relations using SAT and interpolation
|
Jiang, J.-H.R.;Lin, H.-P.;Hung, W.-L.; Jiang, J.-H.R.; Lin, H.-P.; Hung, W.-L.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:11Z |
Hardware Equivalence and Property Verification.
|
Jiang, Jie-Hong Roland;Villa, Tiziano;Crama, Yves;Hammer, Peter L.; Jiang, Jie-Hong Roland; Villa, Tiziano; Crama, Yves; Hammer, Peter L.; JIE-HONG JIANG |
| 臺大學術典藏 |
2020-06-11T06:11:11Z |
Clauses Versus Gates in CEGAR-Based 2QBF Solving.
|
Balabanov, Valeriy;Jiang, Jie-Hong Roland;Mishchenko, Alan;Scholl, Christoph; Balabanov, Valeriy; Jiang, Jie-Hong Roland; Mishchenko, Alan; Scholl, Christoph; JIE-HONG JIANG |
