臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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Institution	Date	Title	Author
臺大學術典藏	2021-09-02T00:05:34Z	Time multiplexing via circuit folding	Chien P.-C;Jiang J.-H.R.; Chien P.-C; Jiang J.-H.R.; JIE-HONG JIANG
臺大學術典藏	2021-09-02T00:05:34Z	Symbolic Uniform Sampling with XOR Circuits	Lin Y.-T;Jiang J.-H.R;Kravets V.N.; Lin Y.-T; Jiang J.-H.R; Kravets V.N.; JIE-HONG JIANG
臺大學術典藏	2021-09-02T00:05:33Z	SFO: A scalable approach to fanout-bounded logic synthesis for emerging technologies	Zhang H.-T;Jiang J.-H.R.; Zhang H.-T; Jiang J.-H.R.; JIE-HONG JIANG
臺大學術典藏	2021-09-02T00:05:33Z	Symbolic gas vulnerability detection and attack synthesis	Peng M.H;Yu F;Jiang J.H.R.; Peng M.H; Yu F; Jiang J.H.R.; JIE-HONG JIANG
臺大學術典藏	2021-09-02T00:05:33Z	SAT-Based On-Track Bus Routing	Zhang H.-T;Fujita M;Cheng C.-K;Jiang J.-H.R.; Zhang H.-T; Fujita M; Cheng C.-K; Jiang J.-H.R.; JIE-HONG JIANG
臺大學術典藏	2021-09-02T00:05:33Z	Symbolic gas vulnerability detection and attack synthesis	Peng M.H;Yu F;Jiang J.H.R.; Peng M.H; Yu F; Jiang J.H.R.; JIE-HONG JIANG
臺大學術典藏	2021-09-02T00:05:32Z	Circuit learning for logic regression on high dimensional boolean space	Chen P.-W;Huang Y.-C;Lee C.-L;Jiang J.-H.R.; Chen P.-W; Huang Y.-C; Lee C.-L; Jiang J.-H.R.; JIE-HONG JIANG
臺大學術典藏	2021-09-02T00:05:32Z	Constraint Solving for Synthesis and Verification of Threshold Logic Circuits	Lee N.-Z;Jiang J.-H.R.; Lee N.-Z; Jiang J.-H.R.; JIE-HONG JIANG
臺大學術典藏	2021-09-02T00:05:32Z	Mining Biochemical Circuits from Enzyme Databases via Boolean Reasoning	Lin Y.-C;Jiang J.-H.R.; Lin Y.-C; Jiang J.-H.R.; JIE-HONG JIANG
臺大學術典藏	2021-09-02T00:05:32Z	Homing Sequence Derivation with Quantified Boolean Satisfiability	Tu K;Wang H;Jiang J.R;Kushik N;Yevtushenko N.; Tu K; Wang H; Jiang J.R; Kushik N; Yevtushenko N.; JIE-HONG JIANG

Showing items 1-10 of 179 (18 Page(s) Totally)
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