| 臺大學術典藏 |
2019-10-24T07:43:08Z |
Homing Sequence Derivation with Quantified Boolean Satisfiability
|
JIE-HONG JIANG;Natalia Kushik;Jie-Hong R. Jiang;Kuan-Hua Tu;Hung-En Wang; Hung-En Wang; Kuan-Hua Tu; Jie-Hong R. Jiang; Natalia Kushik; JIE-HONG JIANG |
| 臺大學術典藏 |
2019-10-24T07:43:08Z |
Sequential Engineering Change Order under Retiming and Resynthesis
|
JIE-HONG JIANG;Jie-Hong R. Jiang;Victor Kravets;Nian-Ze Lee; Nian-Ze Lee; Victor Kravets; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2019-10-24T07:43:08Z |
Sequential Engineering Change Order under Retiming and Resynthesis
|
JIE-HONG JIANG;Jie-Hong R. Jiang;Victor Kravets;Nian-Ze Lee; Nian-Ze Lee; Victor Kravets; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2019-10-24T07:43:08Z |
RecombinaseBased Genetic Circuit Optimization
|
JIE-HONG JIANG;Francois Fages;Jie-Hong Jiang;Chun-Ning Lai; Chun-Ning Lai; Jie-Hong Jiang; Francois Fages; JIE-HONG JIANG |
| 臺大學術典藏 |
2019-10-24T07:43:08Z |
RecombinaseBased Genetic Circuit Optimization
|
JIE-HONG JIANG;Francois Fages;Jie-Hong Jiang;Chun-Ning Lai; Chun-Ning Lai; Jie-Hong Jiang; Francois Fages; JIE-HONG JIANG |
| 臺大學術典藏 |
2019-10-24T07:43:08Z |
RecombinaseBased Genetic Circuit Optimization
|
JIE-HONG JIANG;Francois Fages;Jie-Hong Jiang;Chun-Ning Lai; Chun-Ning Lai; Jie-Hong Jiang; Francois Fages; JIE-HONG JIANG |
| 臺大學術典藏 |
2019-10-24T07:43:08Z |
RecombinaseBased Genetic Circuit Optimization
|
JIE-HONG JIANG;Francois Fages;Jie-Hong Jiang;Chun-Ning Lai; Chun-Ning Lai; Jie-Hong Jiang; Francois Fages; JIE-HONG JIANG |
| 臺大學術典藏 |
2019-10-24T07:43:07Z |
A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning
|
JIE-HONG JIANG;Jie-Hong R. Jiang;Mei-Yen Chiu;Hsiao-Lei Chien; Hsiao-Lei Chien; Mei-Yen Chiu; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2019-10-24T07:43:07Z |
A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning
|
JIE-HONG JIANG;Jie-Hong R. Jiang;Mei-Yen Chiu;Hsiao-Lei Chien; Hsiao-Lei Chien; Mei-Yen Chiu; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2019-10-24T07:43:07Z |
Towards Formal Evaluation and Verification of Probabilistic Design
|
JIE-HONG JIANG;Jie-Hong R. Jiang;Nian-Ze Lee; Nian-Ze Lee; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2019-10-24T07:43:07Z |
Towards Formal Evaluation and Verification of Probabilistic Design
|
JIE-HONG JIANG;Jie-Hong R. Jiang;Nian-Ze Lee; Nian-Ze Lee; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2019-10-24T07:43:07Z |
Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits
|
JIE-HONG JIANG;Jie-Hong R. Jiang;Yi-Hsiang Lai;Hao-Yuan Kuo;Nian-Ze Lee; Nian-Ze Lee; Hao-Yuan Kuo; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2019-10-24T07:43:07Z |
Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits
|
JIE-HONG JIANG;Jie-Hong R. Jiang;Yi-Hsiang Lai;Hao-Yuan Kuo;Nian-Ze Lee; Nian-Ze Lee; Hao-Yuan Kuo; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T15:36:37Z |
Design Partitioning for Large Scale Equivalence Checking and Functional Correction
|
Grace Wu; Yi-Tin Sun; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T15:36:37Z |
2QBF: Challenges and Solutions
|
Valeriy Balabanov;Jie-Hong Rol;Jiang, Christoph Scholl;Alan Mishchenko;Robert K. Brayton; Valeriy Balabanov; Jie-Hong Rol; Jiang, Christoph Scholl; Alan Mishchenko; Robert K. Brayton; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T15:36:37Z |
String Analysis via Automata Manipulation with Logic Circuit Representation
|
Hung-En Wang; Tzung-Lin Tsai; Chun-Han Lin; Fang Yu; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T15:33:10Z |
Simultaneous EUV flare variation minimization and CMP control by coupling-aware dummification
|
Chiang, H.-J.K.; Liu, C.-Y.; Jiang, J.-H.R.; Chang, Y.-W.; Chiang, H.-J.K.; Liu, C.-Y.; Jiang, J.-H.R.; Chang, Y.-W.; YAO-WEN CHANG; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T15:26:17Z |
Efficient Extraction of QBF (Counter)models from Long-Distance Resolution Proofs
|
Valeriy Balabanov;Jie-Hong R. Jiang;Mikolas Janota;Magdalena Widl; Valeriy Balabanov; Jie-Hong R. Jiang; Mikolas Janota; Magdalena Widl; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T15:26:17Z |
Scalable Sequence-Constrained Retention Register Minimization in Power Gating Design
|
JIE-HONG JIANG; Ting-Wei Chiang;Kai-Hui Chang;Yen-Ting Liu;Jie-Hong R. Jiang; Ting-Wei Chiang; Kai-Hui Chang; Yen-Ting Liu; Jie-Hong R. Jiang |
| 臺大學術典藏 |
2018-09-10T15:26:17Z |
Reconfigurable neuromorphic computation in biochemical systems
|
Hui-Ju Katherine Chiang;Jie-Hong R. Jiang;Francois Fages; Hui-Ju Katherine Chiang; Jie-Hong R. Jiang; Francois Fages; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T15:26:17Z |
QELL: QBF Reasoning with Extended Clause Learning and Levelized SAT Solving
|
Kuan-Hua Tu;Tzu-Chen Hsu;Jie-Hong R. Jiang; Kuan-Hua Tu; Tzu-Chen Hsu; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T15:26:17Z |
A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines
|
Yi-Hsiang Lai;Chi-Chuan Chuang;Jie-Hong R. Jiang; Yi-Hsiang Lai; Chi-Chuan Chuang; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T15:26:17Z |
SPOCK: Static performance analysis and deadlock verification for efficient asynchronous circuit synthesis
|
Chun-Hong Shih;Yi-Hsiang Lai;Jie-Hong R. Jiang; Chun-Hong Shih; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T15:26:17Z |
Asynchronous QDI Circuit Synthesis from Signal Transition Protocols
|
Bo-Yuan Huang;Yi-Hsiang Lai;Jie-Hong R. Jiang; Bo-Yuan Huang; Yi-Hsiang Lai; Jie-Hong R. Jiang; JIE-HONG JIANG |
| 臺大學術典藏 |
2018-09-10T15:26:17Z |
Deriving Compositionally Deadlock-free Componenets over Synchronous Automata Compositions
|
Nina Yevtushenko;Khaled El-Fakih;Tiziano Villa;Jie-Hong R. Jiang; Nina Yevtushenko; Khaled El-Fakih; Tiziano Villa; Jie-Hong R. Jiang; JIE-HONG JIANG |
