臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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Institution	Date	Title	Author
國立交通大學	2014-12-12T02:27:35Z	以程式軌跡支援開發X86指令集處理器前端並行方式	邱日清; Jih-ching Chiu; 鍾崇斌; Chung-Ping Chung
國立中山大學	2010-01	Novel instruction stream buffer for VLIW architectures	Jih-Ching Chiu;Kai-Ming Yang
國立中山大學	2009-11	The Optimal Design for Motion Estimation Algorithm on Cell Processor Architecture	Jih-Ching Chiu;Ta-Li Yeh;Cheng-Han Liu; 邱日清;葉大立;劉政翰
國立中山大學	2009-11	A Design of ZigbeeRouting for Street Light Control System	Yeou-Der Chen;Hsiao-Wen Yu;Ming-Shiou Wu;Jih-Ching Chiu; 陳有德;于曉雯;吳明修;邱日清
國立中山大學	2009-11	Data Tunnel in DDRxMemory Controller	Jih-Ching Chiu; Kai-Ming Yang; 邱日清;楊凱名
國立中山大學	2009-09	The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA	Jih-Ching Chiu;Yu-Liang Chou;Tseng-Kuei Lin
國立中山大學	2009-09	The Rendezvous Mechanism for the Multi-Core AMBA System	Jih-Ching Chiu;Kai-Ming Yang;Mu-Chi Chang
國立中山大學	2009-08	The Software and Hardware Integration Linker for Reconfigurable Embedded System	Jih-Ching Chiu;Ta-Li Yeh;Mun-Kit Leong
國立中山大學	2009-06	Design of a Novel SIMD Architecture by Fusing Operations and Registers	Jih-Ching Chiu;Kai-Ming Yang;Yu-Liang Chou
國立中山大學	2009	以嵌入式Linux為背景設計並實現軟硬體協同設計平台	邱日清; Jih-Ching Chiu
國立中山大學	2009	以ZigBee 無線網路為背景之遠端監控系統之設計與實現	邱日清; Jih-Ching Chiu
國立中山大學	2008-08	Designs of the Basic Block Reassembling Instruction Stream Buffer for X86 ISA	Jih-Ching Chiu;Yu-Liang Chou;Ta-Li Yeh;Tseng-Kuei Lin
國立中山大學	2008-05	The Multi-context Reconfigurable Processing Unit for Fine-grain Computing	Jih-Ching Chiu;Yu-Liang Chou;Ren-Bang Lin
國立中山大學	2007-08	Register Processor for MMX instructions	Jih-Ching Chiu;Shou-Xi Hong;Kai-Ming Yang
國立中山大學	2007-08	Compact Dual-Core Architecture	Jih-Ching Chiu;Yu-Liang Chou
國立中山大學	2006-12	A Superscalar Dual-Core Architecture for ARM ISA	Jih-Ching Chiu;Yu-Liang Chou;Po-Kai Chen
國立中山大學	2006-03	An Instruction Scheduling Algorithm and Loop Elimination Methodology for DVBT DSP	Jih-ching Chiu;Jou-you Chen
國立中山大學	2005-11	Design of a DSP for Improving FFT Computing with the Vectorized Mechanisms	Te-Shin Yang;Chun-Hsien Lee;Jih-Ching Chiu
國立中山大學	2005-10	FMRPU: Design of Fine-grain Multi-context Reconfigurable Processing Unit	Jih-ching Chiu;Ren-Bang Lin
國立中山大學	2003-03	Vectorized Code Scheduling Method for the FFT Algorithm in VLIW Architecture	Te-Shin Yang;Jih-Ching Chiu
國立中山大學	2003	Data Item Placement for Load and Storage Balancing	Yung-Cheng Ma;Jih-Ching Chiu;Tien-Fu Chen;Chung-Ping Chung
國立中山大學	2002	Design of Instruction Address Queue for High Degree X86 Superscalar Architectures	Jih-Ching Chiu;Michael Jin-Yi Wang;Chung-Ping Chung
國立中山大學	2001	High-Bandwidth X86 Instruction Fetching Based on Instruction Pointer Table	Jih-Ching Chiu;Chung-Ping Chung
國立中山大學	2000-12	The Fetch Mechanism Issue Of X86 Superscalar Processors with Fetch Rules	Jih-Ching Chiu;Chung-Ping Chung
國立中山大學	2000-12	Improving ILP with Semantic Analyzer for Loop Unrolling in x86 Architectures	Jih-Ching Chiu;Zh-Lung Chen;Jean Jyh-Jiun Shann

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