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Institution	Date	Title	Author
國立中山大學	2009	以ZigBee 無線網路為背景之遠端監控系統之設計與實現	邱日清; Jih-Ching Chiu
國立中山大學	2008-08	Designs of the Basic Block Reassembling Instruction Stream Buffer for X86 ISA	Jih-Ching Chiu;Yu-Liang Chou;Ta-Li Yeh;Tseng-Kuei Lin
國立中山大學	2008-05	The Multi-context Reconfigurable Processing Unit for Fine-grain Computing	Jih-Ching Chiu;Yu-Liang Chou;Ren-Bang Lin
國立中山大學	2007-08	Register Processor for MMX instructions	Jih-Ching Chiu;Shou-Xi Hong;Kai-Ming Yang
國立中山大學	2007-08	Compact Dual-Core Architecture	Jih-Ching Chiu;Yu-Liang Chou
國立中山大學	2006-12	A Superscalar Dual-Core Architecture for ARM ISA	Jih-Ching Chiu;Yu-Liang Chou;Po-Kai Chen
國立中山大學	2006-03	An Instruction Scheduling Algorithm and Loop Elimination Methodology for DVBT DSP	Jih-ching Chiu;Jou-you Chen
國立中山大學	2005-11	Design of a DSP for Improving FFT Computing with the Vectorized Mechanisms	Te-Shin Yang;Chun-Hsien Lee;Jih-Ching Chiu
國立中山大學	2005-10	FMRPU: Design of Fine-grain Multi-context Reconfigurable Processing Unit	Jih-ching Chiu;Ren-Bang Lin
國立中山大學	2003-03	Vectorized Code Scheduling Method for the FFT Algorithm in VLIW Architecture	Te-Shin Yang;Jih-Ching Chiu
國立中山大學	2003	Data Item Placement for Load and Storage Balancing	Yung-Cheng Ma;Jih-Ching Chiu;Tien-Fu Chen;Chung-Ping Chung
國立中山大學	2002	Design of Instruction Address Queue for High Degree X86 Superscalar Architectures	Jih-Ching Chiu;Michael Jin-Yi Wang;Chung-Ping Chung
國立中山大學	2001	High-Bandwidth X86 Instruction Fetching Based on Instruction Pointer Table	Jih-Ching Chiu;Chung-Ping Chung
國立中山大學	2000-12	The Fetch Mechanism Issue Of X86 Superscalar Processors with Fetch Rules	Jih-Ching Chiu;Chung-Ping Chung
國立中山大學	2000-12	Improving ILP with Semantic Analyzer for Loop Unrolling in x86 Architectures	Jih-Ching Chiu;Zh-Lung Chen;Jean Jyh-Jiun Shann
國立中山大學	2000-09	Design of instruction stream buffer with trace support for X86 processors	Jih-Ching Chiu;I-Huan Huang;Chung-Ping Chung
國立中山大學	2000	The Design of the Decoding Unit with High Issue Rate for an X86 Superscalar Microprocessor	R-Ming Shiu;Jih-Ching Chiu;Shin-Ki Cheng;Jyh-Jiun Shann
國立中山大學	1999-05	Survey of Instruction Fetch/Decode Unit and Data Load/Store Unit of X86 Superscalar Microprocessors	R-Ming Shiu;Jih-Ching Chiu;Yuh-Horng Shiau;Jean Jyh-Jiun Shann;Chung-Ping Chung
國立中山大學	1999-04	Design and Implementation of Instruction Fetch/Decode Unit and Data Load/Store Unit of X86 Superscalar Microprocessors	R-Ming Shiu;Jih-Ching Chiu;Yuh-Horng Shiau;Jean Jyh-Jiun Shann;Chung-Ping Chung
國立中山大學	1997-10	Instruction Cache Prefetching with Extended BTB	Shi-An Chi;R-Ming Shiu;Jih-Ching Chiu;Si-En Chang;Chung-Ping Chung

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