| 臺大學術典藏 |
2022-09-21T23:31:01Z |
Automatic Test Program Generation for Transition Delay Faults in Pipelined Processors
|
Chen, Kai Hsun; Yang, Bo Yi; Liang, Jia Ruei; Chen, Hung Lin; JIUN-LANG HUANG |
| 臺大學術典藏 |
2021-07-15T05:32:57Z |
Opportunities for 2.5/3D Heterogeneous SoC Integration
|
HUI-RU JIANG; YAO-WEN CHANG; JIUN-LANG HUANG; CHUNG-PING CHEN |
| 臺大學術典藏 |
2020-06-11T06:50:43Z |
A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays.
|
Lin, Chen-Wei;Huang, Jiun-Lang; Lin, Chen-Wei; Huang, Jiun-Lang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:42Z |
Structural and optical properties of InGaN/GaN multiple quantum well light emitting diodes grown on (1122) facet GaN/sapphire templates by metalorganic chemical vapor deposition
|
Huang, J.-L.;Wang, L.S.;Lai, Y.-S.;Lee, Y.-C.;Qiu, Z.R.;Liu, S.;Wuu, D.-S.;Feng, Z.C.; Huang, J.-L.; Wang, L.S.; Lai, Y.-S.; Lee, Y.-C.; Qiu, Z.R.; Liu, S.; Wuu, D.-S.; Feng, Z.C.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:42Z |
Time-resolved and temperature-varied photoluminescence studies of InGaN/GaN multiple quantum well structures
|
Feng, Z.C.; JIUN-LANG HUANG; Huang, J.-J.; Liu, L.;Wang, W.;Huang, J.-L.;Hu, X.;Chen, P.;Huang, J.-J.;Feng, Z.C.; Liu, L.; Wang, W.; Huang, J.-L.; Hu, X.; Chen, P. |
| 臺大學術典藏 |
2020-06-11T06:50:41Z |
Guest Editors' Introduction: A Promising Alternative to Conventional Silicon
|
Huang, Jiun-Lang;Cheng, Kwang-Ting; Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:41Z |
Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains
|
Wu, S.;Wang, L.-T.;Wen, X.;Jiang, Z.;Tan, L.;Zhang, Y.;Hu, Y.;Jone, W.-B.;Hsiao, M.S.;Li, J.C.-M.;Huang, J.-L.;Yu, L.; Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; Yu, L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:40Z |
A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction
|
Li, B.-Y.;Huang, J.-L.; Li, B.-Y.; Huang, J.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:40Z |
An FPGA-Based Data Receiver for Digital IC Testing.
|
Huang, Wei-Chen;Hou, Guan-Hao;Huang, Jiun-Lang;Kuo, Terry; Huang, Wei-Chen; Hou, Guan-Hao; Huang, Jiun-Lang; Kuo, Terry; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:39Z |
On pre/post-bond testing and calibrating SAR ADC array in 3-D CMOS imager
|
Huang, X.-L.;Kang, P.-Y.;Huang, J.-L.;Chou, Y.-F.;Lee, Y.-P.;Kwai, D.-M.; Huang, X.-L.; Kang, P.-Y.; Huang, J.-L.; Chou, Y.-F.; Lee, Y.-P.; Kwai, D.-M.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:39Z |
FPAA implementation and validation of an SC integrator leakage measurement technique
|
Du, N.-T.;Huang, J.-L.; Du, N.-T.; Huang, J.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:39Z |
Image-quality-driven metrics for testing and calibrating ADC array in CMOS imagers: A first step
|
Chang, H.-M.;Cheng, K.-T.;Huang, J.-L.; Chang, H.-M.; Cheng, K.-T.; Huang, J.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:38Z |
A robust ADC code hit counting technique.
|
Huang, Jiun-Lang;Chou, Kuo-Yu;Lu, Ming-Huan;Huang, Xuan-Lun; Huang, Jiun-Lang; Chou, Kuo-Yu; Lu, Ming-Huan; Huang, Xuan-Lun; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:38Z |
Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime
|
Chen, K.-H.;Chen, C.-Y.;Huang, J.-L.; Chen, K.-H.; Chen, C.-Y.; Huang, J.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:37Z |
Improved weight assignment for logic switching activity during at-speed test pattern generation
|
Wu, M.-F.;Pan, H.-C.;Wang, T.-H.;Huang, J.-L.;Tsai, K.-H.;Cheng, W.-T.; Wu, M.-F.; Pan, H.-C.; Wang, T.-H.; Huang, J.-L.; Tsai, K.-H.; Cheng, W.-T.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:37Z |
Foreword
|
Wang, S.-J.;Huang, J.-L.; Wang, S.-J.; Huang, J.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:36Z |
Diagnosing integrator leakage of single-bit first-order Δσ modulator using DC input
|
Huang, X.-L.;Yang, C.-Y.;Huang, J.-L.; Huang, X.-L.; Yang, C.-Y.; Huang, J.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:36Z |
Logic and Circuit Simulation
|
Huang, J.-L.;Koh, C.-K.;Cauley, S.F.; Huang, J.-L.; Koh, C.-K.; Cauley, S.F.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:35Z |
Histogram-based calibration of capacitor mismatch and comparator offset for 1-bit/stage pipelined ADCs
|
Huang, X.-L.;Kang, P.-Y.;Yu, Y.-C.;Huang, J.-L.; Huang, X.-L.; Kang, P.-Y.; Yu, Y.-C.; Huang, J.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-06-11T06:50:35Z |
A robust ADC code hit counting technique
|
Huang, J.-L.;Chou, K.-Y.;Lu, M.-H.;Huang, X.-L.; Huang, J.-L.; Chou, K.-Y.; Lu, M.-H.; Huang, X.-L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T15:26:16Z |
Design, automation, and test for low-power and reliable flexible electronics
|
T.-C. Huang;J.-L. Huang;K.-T. Cheng; T.-C. Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T15:26:16Z |
A Test-Application-Count Based Learning Technique for Test Time Reduction
|
G.-Y. Lin;K.-H. Tsai;J.-L. Huang;W.-T. Cheng; G.-Y. Lin; K.-H. Tsai; J.-L. Huang; W.-T. Cheng; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T15:00:40Z |
FPGA-Based Subset Sum Delay Lines
|
C.-Y. Wang;Y.-Y. Chen;J.-L. Huang;X.-L. Huang; C.-Y. Wang; Y.-Y. Chen; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T15:00:40Z |
數位類比轉換器的元素的權重的估算方法、裝置及應用其之逐次逼近暫存 器類比數位轉換器
|
陳弘易;陳昶聿;黃炫倫;黃俊郎; 陳弘易; 陳昶聿; 黃炫倫; 黃俊郎; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
SUCCESSIVE APPROXIMATION REGISTER ADC AND METHOD OF LINEARITY CALIBRATION THEREIN
|
Xuan-Lun Huang;Jiun-Lang Huang; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
SUCCESSIVE APPROXIMATION REGISTER ADC AND METHOD OF LINEARITY CALIBRATION THEREIN
|
Xuan-Lun Huang;Jiun-Lang Huang; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
SUCCESSIVE APPROXIMATION REGISTER ADC AND METHOD OF LINEARITY CALIBRATION THEREIN
|
Xuan-Lun Huang;Jiun-Lang Huang; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
測試圖案最佳化的方法
|
吳孟帆; 黃俊郎; 溫曉青; 宮瀨紘平; JIUN-LANG HUANG; 吳孟帆; 黃俊郎; 溫曉青; 宮瀨紘平 |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
迴路測試架構與方法
|
黃炫倫; 黃俊郎; 林王安; 康平穎; JIUN-LANG HUANG; 黃炫倫; 黃俊郎; 林王安; 康平穎 |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
Fault Scrambling Techniques for Yield Enhancement of Embedded Memories
|
S.-K. Lu;H.-C. Jheng;M. Hashizume;J.-L. Huang;P. Ning; S.-K. Lu; H.-C. Jheng; M. Hashizume; J.-L. Huang; P. Ning; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
METHOD AND APPARATUS FOR EVALUATING WEIGHTING OF ELEMENTS OF DAC AND SAR ADC USING THE SAME
|
Hung-I Chen;Chang-Yu Chen;Xuan-Lun Huang;Jiun-Lang Huang; Hung-I Chen; Chang-Yu Chen; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
METHOD AND APPARATUS FOR EVALUATING WEIGHTING OF ELEMENTS OF DAC AND SAR ADC USING THE SAME
|
Hung-I Chen;Chang-Yu Chen;Xuan-Lun Huang;Jiun-Lang Huang; Hung-I Chen; Chang-Yu Chen; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:53Z |
METHOD AND APPARATUS FOR EVALUATING WEIGHTING OF ELEMENTS OF DAC AND SAR ADC USING THE SAME
|
Hung-I Chen;Chang-Yu Chen;Xuan-Lun Huang;Jiun-Lang Huang; Hung-I Chen; Chang-Yu Chen; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:52Z |
Synergistic reliability and yield enhancement techniques for embedded SRAMs
|
S.-K. Lu;H.-H. Huang;J.-L. Huang;P. Ning; S.-K. Lu; H.-H. Huang; J.-L. Huang; P. Ning; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:52Z |
Improve speed path identification with suspect path expressions
|
J.-L. Huang;K.-H. Tsai;Y.-P. Liu;R. Guo;M. Sharma;W.-T. Cheng; J.-L. Huang; K.-H. Tsai; Y.-P. Liu; R. Guo; M. Sharma; W.-T. Cheng; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:52Z |
A mutual characterization based SAR ADC self-testing technique
|
H.-J. Lin;X.-L. Huang;J.-L. Huang; H.-J. Lin; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:52Z |
A circular pipeline processing based deterministic parallel test pattern generator
|
K.-W. Yeh;J.-L. Huang;H.-J. Chao;L.-T. Wang; K.-W. Yeh; J.-L. Huang; H.-J. Chao; L.-T. Wang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:52Z |
Implementation of programmable delay lines on off-the-shelf FPGAs
|
Y.-Y. Chen;J.-L. Huang;T. Kuo; Y.-Y. Chen; J.-L. Huang; T. Kuo; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:52Z |
An IDDQ-Based Source Driver IC Design-for-Test Technique
|
S.-S. Lin;C.-L. Kao;J.-L. Huang;C.-C. Lee;X.-L. Huang; S.-S. Lin; C.-L. Kao; J.-L. Huang; C.-C. Lee; X.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:52Z |
On guaranteeing capture safety in at-speed scan testing with broadcast-scan-based test compression
|
K. Enokimoto;X. Wen;K. Miyase;J.-L. Huang;S. Kajihara;L.-T. Wang; K. Enokimoto; X. Wen; K. Miyase; J.-L. Huang; S. Kajihara; L.-T. Wang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains,
|
S. Wu;L. T. Wang;X. Wen;W. B. Jone;M. S. Hsiao;F. Li;J. C. M. Li;J. L. Huang; S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:29Z |
An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration
|
X.-L. Huang;J.-L. Huang;H.-I. Chen;C.-Y. Chen;K.-T. Tseng;M.-F. Huang;Y.-F. Chou;D.-M. Kwai; X.-L. Huang; J.-L. Huang; H.-I. Chen; C.-Y. Chen; K.-T. Tseng; M.-F. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:29Z |
A SAR ADC missing-decision level detection and removal technique
|
X.-L. Huang;J.-L. Huang;Y.-F. Chou;D.-M. Kwai; X.-L. Huang; J.-L. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:29Z |
A fault-tolerant PE array based matrix multiplier design
|
B.-Y. Jan;J.-L. Huang; B.-Y. Jan; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:29Z |
A transition isolation scan cell design for low shift and capture power
|
Y.-T. Lin;J.-L. Huang;X. Wen; Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:29Z |
Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications
|
Y.-H. Chou;J.-L. Huang;X.-L. Huang; Y.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:29Z |
顯示器驅動電路之測試裝置
|
李權哲; 黃俊郎; 黃瑞澤; JIUN-LANG HUANG; 李權哲; 黃俊郎; 黃瑞澤 |
| 臺大學術典藏 |
2018-09-10T08:47:22Z |
Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing
|
Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:22Z |
類比數位轉換器
|
���T��; ����A; ���v��; ���T��; ����A; ���v��; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:21Z |
ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling
|
X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG |
