| 臺大學術典藏 |
2018-09-10T09:50:52Z |
A mutual characterization based SAR ADC self-testing technique
|
H.-J. Lin;X.-L. Huang;J.-L. Huang; H.-J. Lin; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:52Z |
A circular pipeline processing based deterministic parallel test pattern generator
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K.-W. Yeh;J.-L. Huang;H.-J. Chao;L.-T. Wang; K.-W. Yeh; J.-L. Huang; H.-J. Chao; L.-T. Wang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:52Z |
Implementation of programmable delay lines on off-the-shelf FPGAs
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Y.-Y. Chen;J.-L. Huang;T. Kuo; Y.-Y. Chen; J.-L. Huang; T. Kuo; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:52Z |
An IDDQ-Based Source Driver IC Design-for-Test Technique
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S.-S. Lin;C.-L. Kao;J.-L. Huang;C.-C. Lee;X.-L. Huang; S.-S. Lin; C.-L. Kao; J.-L. Huang; C.-C. Lee; X.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:50:52Z |
On guaranteeing capture safety in at-speed scan testing with broadcast-scan-based test compression
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K. Enokimoto;X. Wen;K. Miyase;J.-L. Huang;S. Kajihara;L.-T. Wang; K. Enokimoto; X. Wen; K. Miyase; J.-L. Huang; S. Kajihara; L.-T. Wang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:31Z |
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains,
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S. Wu;L. T. Wang;X. Wen;W. B. Jone;M. S. Hsiao;F. Li;J. C. M. Li;J. L. Huang; S. Wu; L. T. Wang; X. Wen; W. B. Jone; M. S. Hsiao; F. Li; J. C. M. Li; J. L. Huang; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:29Z |
An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration
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X.-L. Huang;J.-L. Huang;H.-I. Chen;C.-Y. Chen;K.-T. Tseng;M.-F. Huang;Y.-F. Chou;D.-M. Kwai; X.-L. Huang; J.-L. Huang; H.-I. Chen; C.-Y. Chen; K.-T. Tseng; M.-F. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:29Z |
A SAR ADC missing-decision level detection and removal technique
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X.-L. Huang;J.-L. Huang;Y.-F. Chou;D.-M. Kwai; X.-L. Huang; J.-L. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:29Z |
A fault-tolerant PE array based matrix multiplier design
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B.-Y. Jan;J.-L. Huang; B.-Y. Jan; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:29Z |
A transition isolation scan cell design for low shift and capture power
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Y.-T. Lin;J.-L. Huang;X. Wen; Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:29Z |
Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications
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Y.-H. Chou;J.-L. Huang;X.-L. Huang; Y.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:29Z |
顯示器驅動電路之測試裝置
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李權哲; 黃俊郎; 黃瑞澤; JIUN-LANG HUANG; 李權哲; 黃俊郎; 黃瑞澤 |
| 臺大學術典藏 |
2018-09-10T08:47:22Z |
Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing
|
Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:22Z |
類比數位轉換器
|
���T��; ����A; ���v��; ���T��; ����A; ���v��; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:21Z |
ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling
|
X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:21Z |
Robust Circuit Design for Flexible Electronics
|
T.-C Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:21Z |
A self-testing and calibration method for embedded successive approximation register ADC
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X.-L. Huang; P.-Y. Kang; H.-M. Chang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; C.-W. Wu; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:21Z |
Broadcast test pattern generation considering skew-insertion and partial-serial scan
|
C.-J. Lin; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:21Z |
Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs
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W.-A. Lin; C.-C. Li; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:21Z |
A pre- and post-bond self-testing and calibration methodology for SAR ADC Array in 3-D Imager
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X.-L. Huang; P.-Y. Kang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
CSER: BISER-based concurrent soft-error resilience
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Laung-Terng Wang;Touba, N.A.;Zhigang Jiang;Shianling Wu;Jiun-Lang Huang;Li, J.C.-M.; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
CSER: BISER-based concurrent soft-error resilience
|
Laung-Terng Wang;Touba, N.A.;Zhigang Jiang;Shianling Wu;Jiun-Lang Huang;Li, J.C.-M.; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
CSER: BISER-based concurrent soft-error resilience
|
Laung-Terng Wang;Touba, N.A.;Zhigang Jiang;Shianling Wu;Jiun-Lang Huang;Li, J.C.-M.; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:07Z |
An Error Tolerance Scheme for 3D CMOS Imagers
|
H.-M. Sherman Chang;J.-L. Huang;D.-M. Kwai;K.-T. Tim Cheng;C.-W. Wu; H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:07Z |
A scalable quantitative measure of IR-drop for scan pattern generation
|
M.-F. Wu;K.-H. Tsai;W.-T. Cheng;H.-C. Pan;J.-L. Huang;A. Kifli; M.-F. Wu; K.-H. Tsai; W.-T. Cheng; H.-C. Pan; J.-L. Huang; A. Kifli; JIUN-LANG HUANG |
