| 臺大學術典藏 |
2018-09-10T09:25:29Z |
Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications
|
Y.-H. Chou;J.-L. Huang;X.-L. Huang; Y.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T09:25:29Z |
顯示器驅動電路之測試裝置
|
李權哲; 黃俊郎; 黃瑞澤; JIUN-LANG HUANG; 李權哲; 黃俊郎; 黃瑞澤 |
| 臺大學術典藏 |
2018-09-10T08:47:22Z |
Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing
|
Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:22Z |
類比數位轉換器
|
���T��; ����A; ���v��; ���T��; ����A; ���v��; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:21Z |
ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling
|
X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:21Z |
Robust Circuit Design for Flexible Electronics
|
T.-C Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:21Z |
A self-testing and calibration method for embedded successive approximation register ADC
|
X.-L. Huang; P.-Y. Kang; H.-M. Chang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; C.-W. Wu; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:21Z |
Broadcast test pattern generation considering skew-insertion and partial-serial scan
|
C.-J. Lin; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:21Z |
Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs
|
W.-A. Lin; C.-C. Li; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:47:21Z |
A pre- and post-bond self-testing and calibration methodology for SAR ADC Array in 3-D Imager
|
X.-L. Huang; P.-Y. Kang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
CSER: BISER-based concurrent soft-error resilience
|
Laung-Terng Wang;Touba, N.A.;Zhigang Jiang;Shianling Wu;Jiun-Lang Huang;Li, J.C.-M.; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
CSER: BISER-based concurrent soft-error resilience
|
Laung-Terng Wang;Touba, N.A.;Zhigang Jiang;Shianling Wu;Jiun-Lang Huang;Li, J.C.-M.; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
CSER: BISER-based concurrent soft-error resilience
|
Laung-Terng Wang;Touba, N.A.;Zhigang Jiang;Shianling Wu;Jiun-Lang Huang;Li, J.C.-M.; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:07Z |
An Error Tolerance Scheme for 3D CMOS Imagers
|
H.-M. Sherman Chang;J.-L. Huang;D.-M. Kwai;K.-T. Tim Cheng;C.-W. Wu; H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:07Z |
A scalable quantitative measure of IR-drop for scan pattern generation
|
M.-F. Wu;K.-H. Tsai;W.-T. Cheng;H.-C. Pan;J.-L. Huang;A. Kifli; M.-F. Wu; K.-H. Tsai; W.-T. Cheng; H.-C. Pan; J.-L. Huang; A. Kifli; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:07Z |
Power supply noise reduction in broadcast-based compression environment for at-speed scan testing
|
C.-Y. Liang;M.-F. Wu;J.-L. Huang; C.-Y. Liang; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:06Z |
An Improved Weight Assignment Scheme for IR-Drop-Aware At-Speed Scan Pattern Generation
|
M.-F. Wu;H.-C. Pan;T.-H. Wang;J.-L. Huang;K.-H. Tsai;W.-T. Cheng; M.-F. Wu; H.-C. Pan; T.-H. Wang; J.-L. Huang; K.-H. Tsai; W.-T. Cheng; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:06Z |
A robust ADC code hit counting technique
|
J.-L. Huang;Kuo-Yu Chou;Ming-Huan Lu;Xuan-Lun Huang; J.-L. Huang; Kuo-Yu Chou; Ming-Huan Lu; Xuan-Lun Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:06Z |
3D-PIC: An Error Tolerant 3D CMOS Imager
|
H.-M. Sherman Chang;J.-L. Huang;D.-M. Kwai;K.-T. Tim Cheng;C.-W. Wu; H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:06Z |
An ADC/DAC Loopback Testing Methodology by DAC Output Offsetting and Scaling
|
Xuan-Lun Huang;Jiun-Lang Huang; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:06Z |
An ADC/DAC Loopback Testing Methodology by DAC Output Offsetting and Scaling
|
Xuan-Lun Huang;Jiun-Lang Huang; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:06Z |
An ADC/DAC Loopback Testing Methodology by DAC Output Offsetting and Scaling
|
Xuan-Lun Huang;Jiun-Lang Huang; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:04Z |
Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC
|
X.-L. Huang;Yuan-Chi Yu;Jiun-Lang Huang; X.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:04Z |
Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC
|
X.-L. Huang;Yuan-Chi Yu;Jiun-Lang Huang; X.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:04Z |
Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC
|
X.-L. Huang;Yuan-Chi Yu;Jiun-Lang Huang; X.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG |
