| 臺大學術典藏 |
2018-09-10T08:19:10Z |
CSER: BISER-based concurrent soft-error resilience
|
Laung-Terng Wang;Touba, N.A.;Zhigang Jiang;Shianling Wu;Jiun-Lang Huang;Li, J.C.-M.; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
CSER: BISER-based concurrent soft-error resilience
|
Laung-Terng Wang;Touba, N.A.;Zhigang Jiang;Shianling Wu;Jiun-Lang Huang;Li, J.C.-M.; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:10Z |
CSER: BISER-based concurrent soft-error resilience
|
Laung-Terng Wang;Touba, N.A.;Zhigang Jiang;Shianling Wu;Jiun-Lang Huang;Li, J.C.-M.; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; Li, J.C.-M.; CHIEN-MO LI; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:07Z |
An Error Tolerance Scheme for 3D CMOS Imagers
|
H.-M. Sherman Chang;J.-L. Huang;D.-M. Kwai;K.-T. Tim Cheng;C.-W. Wu; H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:07Z |
A scalable quantitative measure of IR-drop for scan pattern generation
|
M.-F. Wu;K.-H. Tsai;W.-T. Cheng;H.-C. Pan;J.-L. Huang;A. Kifli; M.-F. Wu; K.-H. Tsai; W.-T. Cheng; H.-C. Pan; J.-L. Huang; A. Kifli; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:07Z |
Power supply noise reduction in broadcast-based compression environment for at-speed scan testing
|
C.-Y. Liang;M.-F. Wu;J.-L. Huang; C.-Y. Liang; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:06Z |
An Improved Weight Assignment Scheme for IR-Drop-Aware At-Speed Scan Pattern Generation
|
M.-F. Wu;H.-C. Pan;T.-H. Wang;J.-L. Huang;K.-H. Tsai;W.-T. Cheng; M.-F. Wu; H.-C. Pan; T.-H. Wang; J.-L. Huang; K.-H. Tsai; W.-T. Cheng; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:06Z |
A robust ADC code hit counting technique
|
J.-L. Huang;Kuo-Yu Chou;Ming-Huan Lu;Xuan-Lun Huang; J.-L. Huang; Kuo-Yu Chou; Ming-Huan Lu; Xuan-Lun Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:06Z |
3D-PIC: An Error Tolerant 3D CMOS Imager
|
H.-M. Sherman Chang;J.-L. Huang;D.-M. Kwai;K.-T. Tim Cheng;C.-W. Wu; H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:06Z |
An ADC/DAC Loopback Testing Methodology by DAC Output Offsetting and Scaling
|
Xuan-Lun Huang;Jiun-Lang Huang; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:06Z |
An ADC/DAC Loopback Testing Methodology by DAC Output Offsetting and Scaling
|
Xuan-Lun Huang;Jiun-Lang Huang; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T08:19:06Z |
An ADC/DAC Loopback Testing Methodology by DAC Output Offsetting and Scaling
|
Xuan-Lun Huang;Jiun-Lang Huang; Xuan-Lun Huang; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:04Z |
Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC
|
X.-L. Huang;Yuan-Chi Yu;Jiun-Lang Huang; X.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:04Z |
Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC
|
X.-L. Huang;Yuan-Chi Yu;Jiun-Lang Huang; X.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:04Z |
Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC
|
X.-L. Huang;Yuan-Chi Yu;Jiun-Lang Huang; X.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:04Z |
A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition Method
|
K.-W. Yeh;M.-F. Wu;J.-L. Huang; K.-W. Yeh; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:04Z |
A Self-Testing Assisted Pipelined-ADC Calibration Technique
|
J.-L. Huang;X.-L. Huang;P.-Y. Kang; J.-L. Huang; X.-L. Huang; P.-Y. Kang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:04Z |
An On-Chip Integrator Leakage Characterization Technique and Its Applications to Switched Capacitor Circuits Testing
|
C.-Y. Yang;X.-L. Huang;J.-L. Huang; C.-Y. Yang; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:04Z |
Analog-to-Digital Converter
|
Jiun-Lang Huang;Jui-Jer Huang;Chuan-Che Lee; Jiun-Lang Huang; Jui-Jer Huang; Chuan-Che Lee; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:04Z |
Analog-to-Digital Converter
|
Jiun-Lang Huang;Jui-Jer Huang;Chuan-Che Lee; Jiun-Lang Huang; Jui-Jer Huang; Chuan-Che Lee; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:04Z |
Analog-to-Digital Converter
|
Jiun-Lang Huang;Jui-Jer Huang;Chuan-Che Lee; Jiun-Lang Huang; Jui-Jer Huang; Chuan-Che Lee; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:03Z |
A DfT Technique for Diagnosing Integrator Leakage of Single-Bit First-Order Delta-Sigma Modulator Using DC Input
|
X.-L. Huang;C.-Y. Yang;J.-L. Huang; X.-L. Huang; C.-Y. Yang; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:03Z |
Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment
|
M.-F. Wu;J.-L. Huang;X. Wen;K. Miyase; M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:03Z |
LPTest: A Flexible Low-Power Test Pattern Generator
|
M.-F. Wu;K.-S. Hu;J.-L. Huang; M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG |
| 臺大學術典藏 |
2018-09-10T07:43:03Z |
Specification back-propagation and its application to fault simulation of analog/mixed-signal circuits
|
J. L. Huang; C. Y. Pan; K. T. (Tim) Cheng; JIUN-LANG HUANG |
