臺灣學術機構典藏系統 (Taiwan Academic Institutional Repository, TAIR)

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	2019臺灣學術機構典藏研討會
	機構典藏系統RC7版本已發佈

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	機構典藏計畫網站
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	臺大學術典藏NTU Scholars

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Institution	Date	Title	Author
臺大學術典藏	2018-09-10T07:09:28Z	PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Testing in Huffman Coding Test Compression Environment	Y.-T. Lin;M.-F. Wu;J.-L. Huang; Y.-T. Lin; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:28Z	A Segmented a-Si Gate Driver Design for Power Reduction and Floating Gate Line Stabilization	P.-H. Chiu;J.-L. Huang; P.-H. Chiu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:27Z	A Self-Testing and Calibration Technique for Current-Steering DACs	Y.-L. Ma; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T07:09:27Z	Design of a Fault Tolerant Carry Lookahead Adder	C.-Y. Huang, T.-H. Ko; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:37:50Z	A Low Cost Spectral Power Extraction Technique for RF Transceiver Testing	T.-L. Hung; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:37:50Z	An Efficient Peak Power Reduction Technique for Scan Testing	M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	A routability constrained scan chain ordering technique for test power reduction	X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	A period tracking based on-chip sinusoidal jitter extraction technique	C.-Y. Kuo; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance Testing	S.-W. Chang; J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:14Z	A Random Jitter Extraction Technique in the Presence of Sinusoidal Jitter	J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T06:03:13Z	On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines	J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T05:29:18Z	A Fabrication Process Variation Based Approach to Evaluate Design-for-Test Techniques	Y. R. Chen; J. L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T05:29:18Z	An On-Chip Random Jitter Testing Technique Using Low Tap-Count Delay Lines	J. L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T05:29:18Z	Random jitter testing using low tap-count delay lines	J.-L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T04:59:50Z	An Infrastructure IP for On-Chip Clock Jitter Measurement	J. J. Huang; J. L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T04:36:02Z	A Delay-Line Based On-Chip Jitter Measurement Technique	J. J. Huang; J. L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T04:36:02Z	A Low-Cost Jitter Measurement Technique for BIST Applications	J. J. Huang; J. L. Huang; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T04:15:41Z	Testing Second-Order Delta-Sigma Modulators using Pseudo-Random Patterns	C. K. Ong; J. L. Huang; K. T. Cheng; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T04:15:41Z	On-Chip Analog Response Extraction with 1-Bit Sigma-Delta Modulators	H. C. Hong; J. L. Huang; K. T. Cheng; C. W. Wu; JIUN-LANG HUANG
臺大學術典藏	2018-09-10T03:50:56Z	An on-chip short-time interval measurement technique for testing high-speed communication links	J.L. Huang; K.T. Cheng; JIUN-LANG HUANG
臺大學術典藏	2014-09	逐次逼近暫存器類比數位轉換器及其線性度校正的方法	JIUN-LANG HUANG; ��; ��T��; �L��w; �d��o; JIUN-LANG HUANG
臺大學術典藏	2014-09	逐次逼近暫存器類比數位轉換器及其線性度校正的方法	JIUN-LANG HUANG; ��; ��T��; �L��w; �d��o; JIUN-LANG HUANG
臺大學術典藏	2014-02	生成裝置、判別方法、生成方法及びプログラム	JIUN-LANG HUANG; �c�u�T��; �ž�C; \|��T��; �d�s�; JIUN-LANG HUANG
臺大學術典藏	2014-02	生成裝置、判別方法、生成方法及びプログラム	JIUN-LANG HUANG; �c�u�T��; �ž�C; \|��T��; �d�s�; JIUN-LANG HUANG
臺大學術典藏	2013-03	A Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers	D.-M. Kwai; K.-T. Cheng; C.-W. Wu; JIUN-LANG HUANG; J.-L. Huang; H.-M. Chang; H.-M. Chang;J.-L. Huang;D.-M. Kwai;K.-T. Cheng;C.-W. Wu

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