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| 臺大學術典藏 |
2020-06-29T01:20:12Z |
Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains
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Wu, S.;Wang, L.-T.;Wen, X.;Jiang, Z.;Tan, L.;Zhang, Y.;Hu, Y.;Jone, W.-B.;Hsiao, M.S.;Li, J.C.-M.;Huang, J.-L.;Yu, L.; Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; Yu, L.; CHIEN-MO LI |
| 臺大學術典藏 |
2020-06-11T06:50:41Z |
Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains
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Wu, S.;Wang, L.-T.;Wen, X.;Jiang, Z.;Tan, L.;Zhang, Y.;Hu, Y.;Jone, W.-B.;Hsiao, M.S.;Li, J.C.-M.;Huang, J.-L.;Yu, L.; Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; Yu, L.; JIUN-LANG HUANG |
| 臺大學術典藏 |
2020-05-04T07:56:38Z |
Segmented bus design for low-power systems
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HSUEH-I LU; Chen, T.F.; Lu, H.-I.; Wang, J.S.; Jone, W.B.; Chen, J.Y. |
| 國立臺灣大學 |
2003-03 |
Design Theory and Implementation for Low-Power Segmented Bus Systems
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Jone, W. B.; Wang, J. S.; Hsu, I. P.; Chen, J. Y. |
| 臺大學術典藏 |
2003 |
Design theory and implementation for low-power segmented bus systems
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HSUEH-I LU; Lu, H.-I.; Hsu, I.P.; Chen, J.-Y.; Wang, J.S.; Jone, W.-B. |
| 國立成功大學 |
2002-08 |
An efficient BIST method for distributed small buffers
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Jone, W. B.; Huang, D. C.; Wu, S. C.; Lee, Kuen-Jong |
| 淡江大學 |
2000-10 |
Tree-Structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits
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Rau, Jiann-chyi; Jone, W.B.; Chang, S.C.; Wu, Y.L. |
| 國立成功大學 |
2000-01 |
Reducing test application time by scan flip-flops sharing
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Chan, S. C.; Lee, Kuen-Jong; Wu, Z. Z.; Jone, W. B. |
Showing items 1-8 of 8 (1 Page(s) Totally)
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