|
"jou j y"的相關文件
顯示項目 1-10 / 11 (共2頁)
1 2 > >>
每頁顯示[10|25|50]項目
| 臺大學術典藏 |
2020-06-11T06:12:57Z |
Efficient coverage-driven stimulus generation using simultaneous SAT solving, with application to SystemVerilog
|
Cheng, A.-C.;Yen, C.-C.;Val, C.G.;Bayless, S.;Hu, A.J.;Jiang, I.H.-R.;Jou, J.-Y.; Cheng, A.-C.; Yen, C.-C.; Val, C.G.; Bayless, S.; Hu, A.J.; Jiang, I.H.-R.; Jou, J.-Y.; HUI-RU JIANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
RLC coupling-aware simulation and on-chip bus encoding for delay reduction
|
Tu, S.-W.; Chang, Y.-W.; Jou, J.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:58:32Z |
Reliable crosstalk-driven interconnect optimization
|
Jiang, I.H.-R.; Pan, S.-R.; Chang, Y.-W.; Jou, J.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T05:23:28Z |
Rlc coupling-Aware simulation for on-chip buses and their encoding for delay reduction
|
Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
RLC effects on worst-case switching pattern for on-chip buses
|
Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:53:44Z |
Layout techniques for on-chip interconnect inductance reduction
|
Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; Tu, S.-W.; Jou, J.-Y.; Chang, Y.-W.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T04:33:02Z |
Simultaneous floorplanning and buffer block planning
|
Hui-Ru Jiang, I.; Chang, Y.-W.; Jou, J.-Y.; Chao, K.-Y.; YAO-WEN CHANG |
| 臺大學術典藏 |
2018-09-10T03:29:37Z |
Crosstalkdriven interconnect optimization by simultaneous gate and wire sizing
|
Jiang, I.H.R.; Chang, Y.W.; Jou, J.Y.; YAO-WEN CHANG |
| 國立臺灣大學 |
2003-05 |
Electrochemical and Resonance Raman Studies of Nitridomanganese(V) Porphyrins in Nonaqueous Solution
|
Jou, J.Y.; Chang, C.H.; Lee, G.H.; Yu Wang; Su, Y.O.; Yeh, W.L.; Cheng, S.H. |
| 國立東華大學 |
2001 |
On-line microwave hydrolysis and immunoaffinity electrospray mass spectrometry in sequential injection analysis for morphine analysis
|
Jou, J-Y; H-C.Shu |
顯示項目 1-10 / 11 (共2頁)
1 2 > >>
每頁顯示[10|25|50]項目
|
