| 國立成功大學 |
2011-08 |
Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis
|
Jou, Jer Min; Lee, Yun-Lung; Wu, Sih-Sian |
| 東方設計學院 |
2008-02-28 |
同時多執行緒處理器的動態指令提取策略
|
孫建明; 林福添; 楊宏偉; 周哲民; (東方技術學院電機工程系); Sun, Chien-Ming; Lin, Fwu-Tian; Yang, Hung-Wei; Jou, Jer-Min |
| 東方設計學院 |
2007-05-18 |
多媒體應用之執行期可重置硬體平台設計
|
Sun, Chien-Ming; Chen, Ming-Kun; Hu, Sheng-Yao; 胡勝耀; Lin, Fwu-Tian; 林福添; Su, Houng-Yi; Jou, Jer-Min; (東方技術學院電機工程系) |
| 國立成功大學 |
2004-07 |
Efficient architectures for the biorthogonal wavelet transform by filter bank and lifting scheme
|
Shiau, Yeu-Horng; Jou, Jer-Min; Liu, Chin-Chi |
| 國立成功大學 |
2003-10 |
A high-performance tree-block pipelining architecture for separable 2-D inverse discrete wavelet transform
|
Shiau, Yeu-Horng; Jou, Jer-Min |
| 國立成功大學 |
2002-12 |
Design of a dynamic pipelined architecture for fuzzy color correction
|
Jou, Jer-Min; Kuang, Shiann-Rong; Shiau, Yeu-Horng; Chen, Ren-Der |
| 國立成功大學 |
2002-12 |
STG-level decomposition and resynthesis of speed-independent circuits
|
Chen, Ren-Der; Jou, Jer-Min |
| 國立彰化師範大學 |
2002-12 |
Design of a dynamic pipelined architecture for fuzzy color correction
|
Jou, Jer-Min; Kuang, Shiann-Rong; Shiau, Yeu-Horng; Chen, Ren-Der |
| 國立彰化師範大學 |
2002-12 |
STG-level decomposition and resynthesis of speed-independent circuits
|
Chen, Ren-Der; Jou, Jer-Min |
| 國立成功大學 |
2002-07 |
A low-cost gray prediction search chip for motion estimation
|
Jou, Jer-Min; Shiau, Yeu-Horng; Chen, Pei-Yin; Kuang, Shiann-Rong |
| 國立成功大學 |
2001-09 |
Dynamic pipeline design of an adaptive binary arithmetic coder
|
Kuang, Shiann-Rong; Jou, Jer-Min; Chen, Ren-Der; Shiau, Yeu-Horng |
| 國立彰化師範大學 |
2001-09 |
Dynamic pipeline design of an adaptive binary arithmetic coder
|
Kuang, Shiann-Rong; Jou, Jer-Min; Chen, Ren-Der; Shiau, Yeu-Horng |
| 國立成功大學 |
2001-04 |
An efficient blocking-matching algorithm based on fuzzy reasoning
|
Chen, Pei-Yin; Jou, Jer-Min |
| 國立成功大學 |
2000-09-01 |
Adaptive arithmetic coding using fuzzy reasoning and grey prediction
|
Chen, Pei-Yin; Jou, Jer-Min |
| 國立成功大學 |
2000-02 |
An adaptive fuzzy logic controller: Its VLSI architecture and applications
|
Jou, Jer-Min; Chen, Pei-Yin; Yang, Sheng-Fu |
| 國立成功大學 |
1999-06 |
Design of low-error fixed-width multipliers for DSP applications
|
Jou, Jer-Min; Kuang, ShiannRong; Chen, RenDer |
| 國立成功大學 |
1999-06 |
A new efficient fuzzy algorithm for color correction
|
Jou, Jer-Min; Kuang, Shiann-Rong; Chen, Ren-Der |
| 國立彰化師範大學 |
1999-06 |
Design of low-error fixed-width multipliers for DSP applications
|
Jou, Jer-Min; Kuang, Shiann-Rong; Chen, Ren-Der |
| 國立彰化師範大學 |
1999-06 |
A new efficient fuzzy algorithm for color correction
|
Jou, Jer-Min; Kuang, Shiann-Rong; Chen, Ren-Der |
| 國立成功大學 |
1998-07 |
The design of an adaptive on-line binary arithmetic-coding chip
|
Kuang, Shiann-Rong; Jou, Jer-Min; Chen, Yuh-Lin |
