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"jou jer min"???jsp.browse.items-by-author.description???
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| 國立成功大學 |
2011-08 |
Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis
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Jou, Jer Min; Lee, Yun-Lung; Wu, Sih-Sian |
| 東方設計學院 |
2008-02-28 |
同時多執行緒處理器的動態指令提取策略
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孫建明; 林福添; 楊宏偉; 周哲民; (東方技術學院電機工程系); Sun, Chien-Ming; Lin, Fwu-Tian; Yang, Hung-Wei; Jou, Jer-Min |
| 東方設計學院 |
2007-05-18 |
多媒體應用之執行期可重置硬體平台設計
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Sun, Chien-Ming; Chen, Ming-Kun; Hu, Sheng-Yao; 胡勝耀; Lin, Fwu-Tian; 林福添; Su, Houng-Yi; Jou, Jer-Min; (東方技術學院電機工程系) |
| 國立成功大學 |
2004-07 |
Efficient architectures for the biorthogonal wavelet transform by filter bank and lifting scheme
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Shiau, Yeu-Horng; Jou, Jer-Min; Liu, Chin-Chi |
| 國立成功大學 |
2003-10 |
A high-performance tree-block pipelining architecture for separable 2-D inverse discrete wavelet transform
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Shiau, Yeu-Horng; Jou, Jer-Min |
| 國立成功大學 |
2002-12 |
Design of a dynamic pipelined architecture for fuzzy color correction
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Jou, Jer-Min; Kuang, Shiann-Rong; Shiau, Yeu-Horng; Chen, Ren-Der |
| 國立成功大學 |
2002-12 |
STG-level decomposition and resynthesis of speed-independent circuits
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Chen, Ren-Der; Jou, Jer-Min |
| 國立彰化師範大學 |
2002-12 |
Design of a dynamic pipelined architecture for fuzzy color correction
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Jou, Jer-Min; Kuang, Shiann-Rong; Shiau, Yeu-Horng; Chen, Ren-Der |
| 國立彰化師範大學 |
2002-12 |
STG-level decomposition and resynthesis of speed-independent circuits
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Chen, Ren-Der; Jou, Jer-Min |
| 國立成功大學 |
2002-07 |
A low-cost gray prediction search chip for motion estimation
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Jou, Jer-Min; Shiau, Yeu-Horng; Chen, Pei-Yin; Kuang, Shiann-Rong |
Showing items 1-10 of 20 (2 Page(s) Totally)
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