| 國立交通大學 |
2014-12-08T15:37:00Z |
ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant Multiplication
|
Lin, Bu-Ching; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:36:43Z |
Scalable Power Management Using Multilevel Reinforcement Learning for Multiprocessors
|
Pan, Gung-Yu; Jou, Jing-Yang; Lai, Bo-Cheng |
| 國立交通大學 |
2014-12-08T15:36:34Z |
Probability-Based Static Scaling Optimization for Fixed Wordlength FFT Processors
|
Lin, Bu-Ching; Shih, Ming-En; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:25:28Z |
Communication-driven task binding for multiprocessor with latency insensitive Network-on-Chip
|
Lin, Liang-Yu; Wang, Cheng-Yeh; Huang, Pao-Jui; Chou, Chih-Chieh; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:25:28Z |
An observability measure to enhance statement coverage metric for proper evaluation of verification completeness
|
Jiang, Tai-Ying; Liu, Chien-Nan Jimmy; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:24:50Z |
Multiple-Fault Diagnosis Using Faulty-Region Identification
|
Tasi, Meng-Jai; Chao, Mango C. -T.; Jou, Jing-Yang; Wu, Meng-Chen |
| 國立交通大學 |
2014-12-08T15:24:37Z |
FSM-based transaction-level functional coverage for interface compliance verification
|
Su, Man-Yun; Shih, Che-Hua; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:24:37Z |
A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication
|
Chen, Chien-Hua; Lee, Geeng-Wei; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:24:33Z |
Thread Affinity Mapping for Irregular Data Access on Shared Cache GPGPU
|
Kuo, Hsien-Kai; Chen, Kuan-Ting; Lai, Bo-Cheng Charles; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:22:04Z |
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay
|
Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:21:46Z |
Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture Considering Inter-Island Delay
|
Huang, Juinn-Dar; Chen, Chia-I; Hsu, Wan-Ling; Lin, Yen-Ting; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:21:44Z |
Design-for-Debug Layout Adjustment for FIB Probing and Circuit Editing
|
Chen, Kuo-An; Chang, Tsung-Wei; Wu, Meng-Chen; Chao, Mango C. -T.; Jou, Jing-Yang; Chen, Sonair |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Mixed Non-Rectangular Block Packing for Non-Manhattan Layout Architectures
|
Wu, Meng-Chen; Chen, Hung-Ming; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:21:18Z |
Equivalence Checking of Scheduling with Speculative Code Transformations in High-Level Synthesis
|
Lee, Chi-Hui; Shih, Che-Hua; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:16:40Z |
On-chip bus encoding for power minimization under delay constraint
|
Lin, Tzu-Wei; Tu, Shang-Wei; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:15:41Z |
RLC coupling-aware simulation and on-chip bus encoding for delay reduction
|
Tu, Shang-Wei; Chang, Yao-Wen; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:15:32Z |
An optimum algorithm for compacting error traces for efficient design error debugging
|
Yen, Chia-Chih; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:15:02Z |
A tableless approach for high-level power modeling using neural networks
|
Hsu, Chih-Yang; Hsieh, Wen-Tsan; Liu, Chien-Nan Jimmy; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:13:35Z |
Observability analysis on HDL descriptions for effective functional validation
|
Jiang, Tai-Ying; Liu, Chien-Nan Jimmy; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:13:33Z |
Hybrid word-length optimization methods of pipelined FFT processors
|
Wang, Cheng-Yeh; Kuo, Chih-Bin; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:11:01Z |
Verification of pin-accurate port connections
|
Lee, Geeng-Wei; Huang, Juinn-Dar; Wang, Chun-Yao; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:10:04Z |
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging
|
Jiang, Tai-Ying; Liu, Chien-Nan Jimmy; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:08:23Z |
A precise bandwidth control arbitration algorithm for hard real-time SoC buses
|
Lin, Bu-Ching; Lee, Geeng-Wei; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:08:09Z |
Performance-Constrained Voltage Assignment in Multiple Supply Voltage SoC Floorplanning
|
Wu, Meng-Chen; Lu, Ming-Ching; Chen, Hung-Ming; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:04:49Z |
A code generation algorithm of crosstalk-avoidance code with memory for low-power on-chip bus
|
Cheng, Kuang-Chin; Jou, Jing-Yang |
