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"jou jing yang"的相关文件
显示项目 91-100 / 110 (共11页)
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每页显示[10|25|50]项目
| 國立交通大學 |
2014-12-08T15:15:41Z |
RLC coupling-aware simulation and on-chip bus encoding for delay reduction
|
Tu, Shang-Wei; Chang, Yao-Wen; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:15:32Z |
An optimum algorithm for compacting error traces for efficient design error debugging
|
Yen, Chia-Chih; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:15:02Z |
A tableless approach for high-level power modeling using neural networks
|
Hsu, Chih-Yang; Hsieh, Wen-Tsan; Liu, Chien-Nan Jimmy; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:13:35Z |
Observability analysis on HDL descriptions for effective functional validation
|
Jiang, Tai-Ying; Liu, Chien-Nan Jimmy; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:13:33Z |
Hybrid word-length optimization methods of pipelined FFT processors
|
Wang, Cheng-Yeh; Kuo, Chih-Bin; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:11:01Z |
Verification of pin-accurate port connections
|
Lee, Geeng-Wei; Huang, Juinn-Dar; Wang, Chun-Yao; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:10:04Z |
Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging
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Jiang, Tai-Ying; Liu, Chien-Nan Jimmy; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:08:23Z |
A precise bandwidth control arbitration algorithm for hard real-time SoC buses
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Lin, Bu-Ching; Lee, Geeng-Wei; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:08:09Z |
Performance-Constrained Voltage Assignment in Multiple Supply Voltage SoC Floorplanning
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Wu, Meng-Chen; Lu, Ming-Ching; Chen, Hung-Ming; Jou, Jing-Yang |
| 國立交通大學 |
2014-12-08T15:04:49Z |
A code generation algorithm of crosstalk-avoidance code with memory for low-power on-chip bus
|
Cheng, Kuang-Chin; Jou, Jing-Yang |
显示项目 91-100 / 110 (共11页)
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