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| 國立臺灣大學 |
2006-10 |
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction
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Tu, Shang-Wei; Chang, Yao-Wen; Jou, Jing-Yang |
| 臺大學術典藏 |
2006-10 |
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction
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Tu, Shang-Wei; Chang, Yao-Wen; Jou, Jing-Yang; Tu, Shang-Wei; Chang, Yao-Wen; Jou, Jing-Yang |
| 國立臺灣大學 |
2006 |
Reliable crosstalk-driven interconnect optimization
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Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang |
| 國立臺灣大學 |
2004 |
Simultaneous Floorplan and Buffer-Block Optimization
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Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; Chao, Kai-Yuan |
| 臺大學術典藏 |
2004 |
Simultaneous Floorplan and Buffer-Block Optimization
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Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; Chao, Kai-Yuan; Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; Chao, Kai-Yuan |
| 國立臺灣大學 |
2003 |
Inductance Modeling for On-Chip Interconnects
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Tu, Shang-Wei; Shen, Wen-Zen; Chang, Yao-Wen; Chen, Tai-Chen; Jou, Jing-Yang |
| 臺大學術典藏 |
2003 |
Inductance Modeling for On-Chip Interconnects
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Chen, Tai-Chen; Jou, Jing-Yang; Tu, Shang-Wei; Shen, Wen-Zen; Chang, Yao-Wen; Chen, Tai-Chen; Jou, Jing-Yang; Tu, Shang-Wei; Shen, Wen-Zen; Chang, Yao-Wen |
| 國立臺灣大學 |
2000 |
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
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Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang |
| 國立臺灣大學 |
1996-11 |
An efficient PRPG strategy by utilizing essential faults
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Huang, Li-Ren; Jou, Jing-Yang; Kuo, Sy-Yen |
| 國立臺灣大學 |
1996-11 |
Easily testable data path allocation using input/output registers
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Huang, Li-Ren; Jou, Jing-Yang; Kuo, Sy-Yen; Liao, Wen-Bin |
Showing items 101-110 of 110 (5 Page(s) Totally)
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