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Showing items 6-15 of 110 (11 Page(s) Totally)
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| 國立交通大學 |
2017-04-21T06:50:05Z |
Accelerating Dynamic Peak Power Analysis Using An Essential-Signal-Based Methodology
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Shih, Che-Hua; Yen, Chia-Chih; Lin, Shen-Tien; Lin, Hermes; Jou, Jing-Yang |
| 國立交通大學 |
2017-04-21T06:49:52Z |
Chain-Based Pin Count Minimization for General-Purpose Digital Microfluidic Biochips
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Lei, Yung-Chun; Hsu, Chen-Shing; Huang, Juinn-Dar; Jou, Jing-Yang |
| 國立交通大學 |
2017-04-21T06:49:29Z |
Resource-Aware Functional ECO Patch Generation
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Cheng, An-Che; Jiang, Iris Hui-Ru; Jou, Jing-Yang |
| 國立交通大學 |
2016-03-28T00:04:19Z |
Scalable Global Power Management Policy Based on Combinatorial Optimization for Multiprocessors
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Pan, Gung-Yu; Yang, Jed; Jou, Jing-Yang; Lai, Bo-Cheng Charles |
| 國立交通大學 |
2015-12-02T02:59:21Z |
Power-Efficient Instancy Aware DRAM Scheduling
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Pan, Gung-Yu; Lai, Chih-Yen; Jou, Jing-Yang; Lai, Bo-Cheng Charles |
| 國立交通大學 |
2015-11-26T01:02:48Z |
使用有效的電路刺激產生法與邏輯修正以加速產品上市時間之研究
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鄭安哲; Cheng, An-Che; 江蕙如; 周景揚; Jiang, Hui-Ru; Jou, Jing-Yang |
| 國立交通大學 |
2015-11-26T00:57:11Z |
在多核心智慧型裝置上結合雲端運算及機器學習演算法所實現的電源管理策略
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潘畊宇; Pan, Gung-Yu; 周景揚; 賴伯承; Jou, Jing-Yang; Lai, Bo-Cheng |
| 國立交通大學 |
2015-07-21T11:21:09Z |
Reducing Contention in Shared Last-Level Cache for Throughput Processors
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Kuo, Hsien-Kai; Lai, Bo-Cheng Charles; Jou, Jing-Yang |
| 國立交通大學 |
2015-07-21T11:21:09Z |
Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilog
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Cheng, An-Che; Yen, Chia-Chih (Jack); Val, Celina G.; Bayless, Sam; Hu, Alan J.; Jiang, Iris Hui-Ru; Jou, Jing-Yang |
| 國立交通大學 |
2015-07-21T08:30:53Z |
A Read-Write Aware DRAM Scheduling for Power Reduction in Multi-Core Systems
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Lai, Chih-Yen; Pan, Gung-Yu; Kuo, Hsien-Kai; Jou, Jing-Yang |
Showing items 6-15 of 110 (11 Page(s) Totally)
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